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Data Manual
March 2007 Digital Audio Video
SLES140A
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the t
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Contents Contents Section Page 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Detailed Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 TVP5147M1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1
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Contents Section Page 2.11.11 Luminance Contrast Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.11.12 Chrominance Saturation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.11.13 Chroma Hue Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.11.14 Chrominance Processing Control 1 Register . . . . . . . . . . . . . . . . .
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Contents Section Page 2.11.59 Analog Output Control 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.11.60 Chip ID MSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.11.61 Chip ID LSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.11.62 CPLL Speed Control Register . . . . . . . . . . . . . . . . . . . . .
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Contents Section Page 3.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.3.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.3.2 Analog Processing and A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.3.3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Illustrations List of Illustrations Figure Title Page 1−1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1−2 Terminal Assignments Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2−1 Analog Processors and A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables List of Tables Table Title Page 1−1 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2−1 Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2−2 Summary of Line Frequencies, Data Rates, and Pixel/Line Counts . . . . . . . . . . . . . . . . . . . . . . . . . 16 2−3 EAV an
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Introduction 1 Introduction The TVP5147M1 device is a high-quality, single-chip digital video decoder that digitizes and decodes all popular baseband analog video formats into digital component video. The TVP5147M1 decoder supports the analog-to-digital (A/D) conversion of component YPbPr signals, as well as the A/D conversion and decoding of NTSC, PAL, and SECAM composite and S-video into component YCbCr. This decoder includes two 10-bit 30-MSPS A/D converters (ADCs). Preceding each ADC in the
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Introduction 1.1 Detailed Functionality • Two 30-MSPS, 10-bit A/D channels with programmable gain control • Supports NTSC (J, M, 4.43), PAL (B, D, G, H, I, M, N, Nc, 60) and SECAM (B, D, G, K, K1, L) CVBS, and S-video • Supports analog component YPbPr video format with embedded sync • 10 analog video input terminals for multisource connection • Supports analog video output • User-programmable video output formats − 10-bit ITU-R BT.656 4:2:2 YCbCr with embedded syncs − 10-bit 4:2:2 YCbCr with sep
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Introduction • VBI data processor − Teletext (NABTS, WST) − CC and extended data service (EDS) − Wide screen signaling (WSS) − Copy generation management system (CGMS) − Video program system (VPS/PDC) − Vertical interval time code (VITC) − Gemstar 1×/2× mode − V-Chip decoding − Register readback of CC, WSS (CGMS), VPS/PDC, VITC and Gemstar 1×/2× sliced data 2 • I C host port interface • Reduced power consumption: 1.8-V digital core, 3.3-V for digital I/O, and 1.8-V/3.3 V analog core with power-
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Introduction 1.5 Functional Block Diagram VBI Copy CVBS/Y Data Protection Detector Processor Analog Front End VI_1_A Composite and S-Video Processor CVBS/ VI_1_B C/Pb Y/C VI_1_C CVBS/Y Y Luma Y[9:0] Separation Processing Output YCbCr 5-line Formatter VI_2_A C Chroma C/CbCr Clamping Adaptive CVBS/ Processing C[9:0] VI_2_B AGC Comb Y VI_2_C M 2 × 11-Bit U ADC VI_3_A X CVBS/ VI_3_B C/Pr VI_3_C CVBS/Y VI_4_A GPIO Sampling Clock Timing Processor Host With Sync Detector Interface Figure 1−1. Functiona
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Introduction 1.6 Terminal Assignments PFP PACKAGE (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VI_1_B 1 60 C_6/GPIO VI_1_C C_7/GPIO 2 59 CH1_A33GND C_8/GPIO 3 58 CH1_A33VDD 4 57 C_9/GPIO CH2_A33VDD DGND 5 56 CH2_A33GND DVDD 6 55 VI_2_A 7 54 Y_0 VI_2_B 8 53 Y_1 VI_2_C Y_2 9 52 CH2_A18GND Y_3 10 51 CH2_A18VDD 11 50 Y_4 A18VDD_REF IOGND 12 49 A18GND_REF IOVDD 13 48 NC 14 47 Y_5 NC 15 46 Y_6 VI_3_A Y_7 16 45 VI_3_B Y_8 17 44 VI_3_C 18 43 Y_9 NC 19 DGND 42 NC DVDD 20 41 21 2
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Introduction 1.7 Terminal Functions Table 1−1. Terminal Functions TERMINAL I/O I/O DESCRIPTION DESCRIPTION NAME NUMBER Analog Video VI_1_A 80 I/O VI_1_A: Analog video input for CVBS/Pb/C or analog video output (see Section 2.11.59) VI_1_B 1 I VI_1_x: Analog video input for CVBS/Pb/C VI_1_C 2 I VI_2_x: Analog video input for CVBS/Y VI_2_A 7 I VI_3_x: Analog video input for CVBS/Pr/C VI_2_B VI_2_B 8 8 II VI_4_A: Analog video input for CVBS/Y VI_4_A: Analog video input for CVBS/Y VI_2_C 9 I Up to 1
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Introduction Table 1−1. Terminal Functions (Continued) TERMINAL I/O I/O DESCRIPTION DESCRIPTION NAME NUMBER Power Supplies AGND 26 Analog ground. Connect to analog ground. A18GND_REF 13 Analog 1.8-V return A18VDD_REF 12 Analog power for reference 1.8 V CH1_A18GND 79 CH2_A18GND 10 Analog 1.8-V return A18GND 24 CH1_A18VDD 78 CH2_A18VDD 11 Analog power. Connect to 1.8 V. A18VDD 25 CH1_A33GND 3 Analog 3.3-V return CH2_A33GND 6 CH1_A33VDD 4 Analog power. Connect to 3.3 V. CH2_A33VDD 5 27, 32, 42, DGN
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Introduction 8 TVP5147M1PFP SLES140A—March 2007
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Functional Description 2 Functional Description 2.1 Analog Processing and A/D Converters Figure 2−1 shows a functional diagram of the analog processors and A/D converters, which provide the analog interface to all video inputs. It accepts up to 10 inputs and performs source selection, video clamping, video amplification, A/D conversion, and gain and offset adjustments to center the digitized video signal. The TVP5147M1 supports one analog video output for the selected analog input video. I/O M V
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Functional Description • Up to 10 selectable individual composite video inputs • Up to four selectable S-video inputs • Up to three selectable analog YPbPr video inputs and one CVBS input • Up to two selectable analog YPbPr video inputs, two S-video inputs, and two CVBS inputs 2 The input selection is performed by the input select register at I C subaddress 00h (see Section 2.11.1). 2.1.2 Analog Input Clamping An internal clamping circuit restores the ac-coupled video signal to a fixed dc level.
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Functional Description 2.2 Digital Video Processing Figure 2−2 is a block diagram of the TVP5147M1 digital video decoder processing. This block receives digitized video signals from the ADCs and performs composite processing for CVBS and S-video inputs and YCbCr signal enhancements for CVBS and S-video inputs. It also generates horizontal and vertical syncs and other output control signals such as genlock for CVBS and S-video inputs. Additionally, it can provide field identification, horizontal
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Functional Description Y Peaking Delay CVBS/Y Line – Delay Y NTSC/PAL Remodulation SECAM Luma Contrast Brightness Cb Saturation Adjust Notch Filter Cr SECAM Color CVBS Demodulation Color LPF Notch U ↓ 2 Filter Burst Accumulator (U) 5-Line Adaptive Comb Filter Burst Notch U Accumulator Delay Filter (V) Notch V Color LPF Delay V Filter ↓ 2 NTSC/PAL CVBS/C Demodulation Figure 2−3. Composite and S-Video Processing Block Diagram 2.2.2.1 Color Low-Pass Filter High filter bandwidth preserves sharp colo
