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ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)
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DS619 (v1.0) September 17, 2007 Product Specification
Introduction
LogiCORE™ Facts
The ChipScope™ PLB IBA core is a specialized Bus Core Specifics
Analyzer core designed to debug embedded systems that
Supported Device Virtex-E, Virtex, Spartan™-3A DSP,
contain the IBM CoreConnect™ Processor Local Bus (PLB)
Family Spartan-3AN, Spartan-3A, Spartan-3E,
Spartan-3, Spartan-IIE, Spartan-II, Virtex-5
version 4.6. The ChipScope PLB46 IBA core i
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R ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a) ChipScope PLB46 IBA I/O Signals Table 1: IBA_PLBv46 Pin Descriptions Port MU Signal Name Interface I/O Description P1 CONTROL ICON I/O Icon control bus IO P2 PLB_Clk System I System Clock P3 MU_1C iba_trigin_in GENERIC I Generic Trigger Inputs P4 iba_trig_out GENERIC O IBA Trigger Output Reset & Error Status P5 MU_1A PLB_Rst System I Registered reset output from arbitration logic P6 MU_1A Bus_Error_Det System I Bus Error Interrupt P7 MU_1A PLB_l
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R ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a) Table 1: IBA_PLBv46 Pin Descriptions (Continued) Port MU Signal Name Interface I/O Description P34 MU_2C PLB_TAttribute[0:15] Slave I PLB Transfer Attribute Address P35 MU_3A PLB_ABus[0:31] Slave I PLB address bus, lower 32 bits P36 MU_3B PLB_UABus[0:31] Slave I PLB address bus, upper 32 bits Data P37 MU_4 PLB_wrDBus[0: C_PLBV46_DWIDTH-1] Slave I PLB write data bus P38 MU_5 PLB_SrdDBus[0: Sim I Output of SL_rdDBus OR gate C_PLBV46_DWIDTH-1] Slave
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R ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a) Table 1: IBA_PLBv46 Pin Descriptions (Continued) Port MU Signal Name Interface I/O Description P58 MU_10 M_abort[0: Master I Master abort bus request indicator C_PLBV46_NUM_MASTERS-1] P59 MU_10 PLB_rdPendPri[0:1] Master I PLB pending read request priority P60 MU_10 PLB_wrPendPri[0:1] Master I PLB pending write request priority P61 MU_10 PLB_rdPendReq Master /Slave I PLB pending bus read request indicator P62 MU_10 PLB_wrPendReq Master /Slave I PLB
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R ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a) a user to look for multiple occurrences of the match event. enabled and defined with unique C_MU_xx_TYPE pattern This counter width is controllable through the match units. C_MU_xx_CNT_W parameter (xx is a place holder for The 6a and 6b match units are used for the slave side 1-13). When this parameter is set to 0 only 1 occurrence is interface. This match unit holds all the control and status counted, otherwise the match event count is limited
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R ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a) Table 2: IBA_PLBv46 Design Parameters (Continued) Default VHDL Generic Feature/Description Parameter Name Allowable Values Value Type G8 PLB Address Bus Width C_PLBV46_AWIDTH 32 32 Integer G9 PLB Data Bus Width C_PLBV46_DWIDTH 32,64,128 64 Integer IBA Storage Options and Trig Out G10 Number of data samples captured for every C_NUM_DATA_SAMPLES 512, 1024, 2048, 1024 Integer trigger match. Note that the range of 4096, 8192, 16384, acceptable value
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R ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a) Table 2: IBA_PLBv46 Design Parameters (Continued) Default VHDL Generic Feature/Description Parameter Name Allowable Values Value Type G30 0=basic, 1=basic w/ edges, C_MU_3_TYPE_ADDR 0,1,2,3,4,5 0 Integer 2=extended, 3= extended w/edges, 4=range, 5=range w/edges G31 Match unit counter width. 0 means do not C_MU_3_CNT_W_ADDR 0,1-32 0 Integer use G32 1=Enable storing MU 3 signals in the data C_MU_3_EN_STORE_ADDR 0,1 1 Integer sample storage buffer.
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R ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a) Table 2: IBA_PLBv46 Design Parameters (Continued) Default VHDL Generic Feature/Description Parameter Name Allowable Values Value Type G46 1=Enable storing MU 6 signals in the data C_MU_6_EN_STORE_SLV_ 0,1 1 Integer sample storage buffer. CTL_BUS 0=Disable C_USE_MU_6A_SLV_CTL or C_USE_MU_6B_SLV_SZ_WADDR must be 1 in order to store. Slave Busy Status G47 USE SI_MBusy signal C_USE_MU_7_SLV_BSY 1,0 0 Integer G48 0=basic, 1=basic w/ edges C_MU_7_TYP
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R ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a) Table 2: IBA_PLBv46 Design Parameters (Continued) Default VHDL Generic Feature/Description Parameter Name Allowable Values Value Type PLB Master Control Bus G63 Use Master Control Signals C_USE_MU_11_MSTR_CTL 1,0 0 Integer G64 Number of match units to use C_MU_11_NUM_MSTR_CTL 1,2 1 Integer G65 0=basic, 1=basic w/ edges C_MU_11_TYPE_MSTR_CTL 0,1 0 Integer G66 Match unit counter width. 0 means do not C_MU_11_CNT_W_MSTR_ 0,1-32 0 Integer use CTL G67
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R ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a) assigned for this match group. When multiple match units Design Implementation are available, sequences of a match unit group can be The ChipScope PLB IBA design is implemented in a Tcl detected. For example, in MU_2, a trigger sequence could script. When the EDK Platgen tool is run, this Tcl script is be created to look for PLB_PAValid=1 followed by a rising called and it internally calls the ChipScope Pro Core edge on PLB_SaddrAck. For this
