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PCI32 Interface v3.0
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DS206 August 31, 2005 Product Specification v3.0.151
Features
LogiCORE Facts
(1)
• Fully PCI 3.0-compliant LogiCORE™, 32-bit, 66/33
PCI32 Resource Utilization
MHz interface
Slice Four Input LUTs 553
Customizable, programmable, single-chip solution
Slice Flip-Flops 566
Pre-defined implementation for predictable timing
IOB Flip-Flops 97
Incorporates Xilinx Smart-IP™ technology
IOBs 50
3.3V operation at 0-66 MHz
TBUFs 288
5.0V operation at 0-33 MHz
(2)
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PCI32 Interface v3.0 Fact Table Notes 1. Resource utilization depends on configuration of the interface and user design. Unused resources are trimmed by the Xilinx technology mapper. The utilization figures reported in this table are representative of a maximum configuration. 2. Designs running at 66 MHz in devices other than Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3, and Spartan-3E require one GCLKIOB and two GCLKs. Virtex-4 implementations require additional BUFG for 200 MHz reference cl
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PCI32 Interface v3.0 Table 1: Core Implementation (Continued) Supported Device Power Supply Spartan™-II XC2S30-PQ208-5C 3.3V, 5.0V only Spartan-II XC2S50-PQ208-5C 3.3V, 5.0V only Spartan-II XC2S100-PQ208-5C 3.3V, 5.0V only Spartan-II XC2S150-PQ208-5C 3.3V, 5.0V only Spartan-II XC2S200-PQ208-5C 3.3V, 5.0V only Spartan-IIE 2S50E-PQ208-6C 3.3V only Spartan-IIE XC2S100E-PQ208-6C 3.3V only Spartan-IIE XC2S150E-PQ208-6C 3.3V only Spartan-IIE XC2S200E-PQ208-6C 3.3V only Spartan-IIE XC2S300E-PQ208-6C
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PCI32 Interface v3.0 Other FPGA resources that can be used in conjunction with the core to enable efficient implementation of a PCI system include: Block SelectRAM™ memory. Blocks of on-chip ultra-fast RAM with synchronous write and dual-port RAM capabilities. Used in PCI designs to implement FIFOs. SelectRAM memory. Distributed on-chip ultra-fast RAM with synchronous write option and dual-port RAM capabilities. Used in PCI designs to implement FIFOs. Internal three-state bus capability
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PCI32 Interface v3.0 Figure 1 illustrates a user application and the PCI Interface partitioned into five major blocks. Figure Top x-ref 1 PAR PAR64 Base Base Base Parity Command/ Address Address Address PERR- Generator/ Status Register Register Register Checker Register SERR- 0 1 2 AD[63:0] ADIO[63:0] ADIO[63:0] FRAME- Interrupt Vendor ID, Latency IRDY- Pin and Rev ID, Timer Initiator Line Other User REQ- Register State Register Data GNT- Machine REQ64- PCI Configuration Space ACK64- TRDY- Targ
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PCI32 Interface v3.0 Target State Machine This block controls the PCI interface target functions. The states implemented are a subset of those defined in Appendix B of the PCI Local Bus Specification. The target control logic uses one-hot encoding for maximum performance. Table 2: PCI Configuration Space Header 31 16 15 0 00h Device ID Vendor ID 04h Status Command 08h Class Code Rev ID 0Ch BIST Header Latency Cache Line Type Timer Size 10h Base Address Register 0 (BAR0) 14h Base Address Regi
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PCI32 Interface v3.0 Bandwidth The PCI Interface supports fully compliant zero wait-state burst operations for both sourcing and receiving data. This interface supports a sustained bandwidth of up to 264 MBytes/sec. The design can be configured to take advantage of the ability of the PCI Interface to do very long bursts. The flexible user application interface, combined with support for many different PCI features, gives users a solution that lends itself to use in many high-performance applicat
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PCI32 Interface v3.0 Timing Specifications The maximum speed at which your user design is capable of running can be affected by the size and quality of the design. The following tables show the key timing parameters for the PCI Interface. Table 4 lists the Timing Parameters in the 66 MHz Implementations and Table 5 lists Timing Parameters in the 33 MHz Implementations. Table 3: PCI Bus Commands PCI PCI CBE [3:0] Command Initiator Target 0000 Interrupt Acknowledge Yes Yes 0001 Special Cycle Yes
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PCI32 Interface v3.0 Table 4: Timing Parameters, 66 MHz Implementations Symbol Parameter Min Max 1 T CLK Cycle Time 15 30 cyc T CLK High Time 6 - high T CLK Low Time 6 - low CLK to Signal Valid Delay 2 2 T 2 6 val (bussed signals) CLK to Signal Valid Delay 2 2 T 2 6 val (point to point signals) 2 T Float to Active Delay 2 - on 1 T Active to Float Delay - 14 off Input Setup Time to CLK 2,3 T 3 - su (bussed signals) Input Setup Time to CLK 2,3 T 5 - su (point to point signals) 2,3 T Input Hold T
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PCI32 Interface v3.0 Ordering Information Build v3.0.150 of the PCI core, with support added for Spartan-3E, is for available for download from the Xilinx IP Center and can also be accessed through the Xilinx CORE Generator system v7.1i or higher. The Xilinx CORE Generator is bundled with the ISE Foundation v7.1i software at no additional charge. To purchase the Xilinx PCI core, please contact your local Xilinx sales representative. Part Numbers DO-DI-PCI32-IP - Access to the v3.0 PCI32 33 MHz
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PCI32 Interface v3.0 Revision History The following table shows the revision history for this document. Date Version Revision 07/30/02 1.2 Style updates 12/18/02 1.3 Updated to build v3.0.103; v5.Ii, 1st feature: 32-bit was 64/32-bit 3/7/03 1.4 Updated to build v3.0.105; v5.2i Updated to build v3.0.106; in LogiCORE Facts table, updated PC32/33 product 4/14/03 1.5 listings to include Spartan-3 device support. 5/8/03 1.6 Updated Xilinx tools to 5.2i SP2; added Note 10. Updated to build v3.0.113
