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ICX274AQ
Diagonal 8.923mm (Type 1/1.8) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX274AQ is a diagonal 8.923mm (Type 1/1.8)
20 pin DIP (Plastic)
interline CCD solid-state image sensor with a square
pixel array and 2.01M effective pixels. Progressive
scan allows all pixels' signals to be output
independently within approximately 1/15 second,
and output is also possible using various addition
and pulse elimination methods. This chip features an
electron
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ICX274AQ Block Diagram and Pin Configuration (Top View) 10 9 8 7 6 5 4 3 2 1 G B G B R G R G G B G B R G R G G B G B R G R G G B G B R G R G Note) Horizontal register Note) : Photo sensor 11 12 13 14 15 16 17 18 19 20 Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 Vφ4 Vertical register transfer clock 11 VDD Supply voltage 2 Vφ3A Vertical register transfer clock 12 φRG Reset gate clock 3 Vφ3B Vertical register transfer clock 13 Hφ2B Horizontal register transfer clo
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ICX274AQ Absolute Maximum Ratings Item Ratings Unit Remarks VDD, VOUT, φRG – φSUB –40 to +12 V Vφ2α, Vφ3α – φSUB (α = A to C) –50 to +15 V Against φSUB Vφ1, Vφ4, VL – φSUB –50 to +0.3 V Hφ1β, Hφ2β, GND – φSUB (β = A, B) –40 to +0.3 V CSUB – φSUB –25 to V VDD, VOUT, φRG, CSUB – GND –0.3 to +22 V Against GND Vφ1, Vφ2α, Vφ3α, Vφ4 – GND (α = A to C) –10 to +18 V Hφ1β, Hφ2β – GND (β = A, B) –10 to +6.5 V Vφ2α, Vφ3α – VL (α = A to C) –0.3 to +28 V Against VL Vφ1, Vφ4, Hφ1β, Hφ2β, GND – VL (β = A, B) –
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ICX274AQ Bias Conditions Item Symbol Min. Typ. Max. Unit Remarks Supply voltage VDD 14.55 15.0 15.45 V ∗3 Protective transistor bias VL ∗1 No line addition VSUB Internally generated value Substrate voltage ∗4 adjustment range ∗2 2-line addition VSUB2 8.8 14.4 V Indicated Indicated Indicated Substrate voltage adjustment accuracy ∆ VSUB V voltage – 0.2 voltage voltage + 0.2 ∗5 Reset gate clock φRG V 1 ∗ Progressive scan mode, 2/8-line readout mode, 2/4-line readout mode, center scan modes (1) and
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ICX274AQ Clock Voltage Conditions Waveform Item Symbol Min. Typ. Max. Unit Remarks diagram Readout clock VVT 14.55 15.0 15.45 V 1 voltage VVH1, VVH2 –0.05 0 0.05 V 2 VVH = (VVH1 + VVH2)/2 VVH3, VVH4 –0.2 0 0.05 V 2 VVL1, VVL2, –8.0 –7.5 –7.0 V 2 VVL = (VVL3 + VVL4)/2 VVL3, VVL4 VφV 6.8 7.5 8.05 V 2 VφV = VVHn – VVLn (n = 1 to 4) Vertical transfer VVH3 – VVH –0.25 0.1 V 2 clock voltage VVH4 – VVH –0.25 0.1 V 2 VVHH 0.5 V 2 High-level coupling VVHL 0.5 V 2 High-level coupling VVLH 0.5 V 2 Low-leve
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ICX274AQ Clock Equivalent Circuit Constants Item Symbol Min. Typ. Max. Unit Remarks CφV1 3300 pF CφV2A, CφV2B 1200 pF Capacitance between vertical transfer clock and CφV2C 2700 pF GND CφV3A, CφV3B 1000 pF CφV3C 1800 pF CφV4 6800 pF CφV12 (A, B) 120 pF CφV12C 220 pF CφV13 (A, B) 150 pF CφV13C 270 pF CφV14 2700 pF CφV2 (A, B), 3 (A, B) 470 pF Capacitance between vertical transfer clocks CφV2 (A, B), 3C 680 pF CφV2 (A, B), 4 680 pF CφV2C, 3 (A, B) 1000 pF CφV2C, 3C 820 pF CφV2C, 4 1800 pF CφV3 (A,
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ICX274AQ Vφ1 RφH RφH Hφ1A Hφ2A R1 CφV1 RφH RφH Hφ1B Hφ2B CφHH CφV14 CφV12α (α = A to C) CφV2α4 (α = A to C) RφH2 CφH1 CφH2 Vφ4 Vφ2α (α = A to C) R4 R2α (α = A to C) RGND CφV4 CφV2α (α = A to C) Horizontal transfer clock equivalent circuit CφV2α3α (α = A to C) CφV3α4 (α = A to C) CφV3α (α = A to C) CφV13α (α = A to C) R3α (α = A to C) RφRG RGφ Vφ3α (α = A to C) CφRG Note 2) Cφ2α2β and Cφ3α3β (α = A to C, β = A to C other than α) are sufficiently small relative to other capacitance between other v
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ICX274AQ Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% φM VVT φM 2 10% 0V 0% tr twh tf (2) Vertical transfer clock waveform Vφ1 Vφ3A, Vφ3B, Vφ3C VVHH VVH1 VVHH VVH VVH VVHH VVHH VVHL VVHL VVHL VVH3 VVHL VVL1 VVL3 VVLH VVLH VVLL VVLL VVL VVL Vφ2A, Vφ2B, Vφ2C Vφ4 VVHH VVHH VVHH VVHH VVH VVH VVHL VVHL VVHL VVHL VVH2 VVH4 VVLH VVLH VVL2 VVLL VVLL VVL VVL4 VVL VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4) – 8 –
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ICX274AQ (3) Horizontal transfer clock waveform tr twh tf Hφ2β 90% VCR VφH twl VφH 2 10% Hφ1β VHL two Cross-point voltage for the Hφ1β rising side of the horizontal transfer clocks Hφ1β and Hφ2β waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks Hφ1β and Hφ2β is two. (β = A, B) (4) Reset gate clock waveform tr twh tf VRGH RG waveform twl VφRG Point A VRGLH VRGL VRGLL VRGLm VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during th
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ICX274AQ Clock Switching Characteristics (Horizontal drive frequency: 28.6364MHz) twh twl tr tf Item Symbol Unit Remarks Min. Typ. Max.Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. During Readout clock VT 3.3 3.5 0.5 0.5 µs readout Vφ1, Vφ4, Vertical transfer ∗1 Vφ2α, Vφ3α 15 400 ns clock (α = A to C) Hφ1β (β = A, B) 10 12.5 10 12.5 5 7.5 5 7.5 Horizontal ∗2 ns transfer clock Hφ2β (β = A, B) 10 12.5 10 12.5 5 7.5 5 7.5 ns Reset gate clock φRG 4 7 24 2 3 During drain Substrate clock φSUB 2.1 0.5 0
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ICX274AQ Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics) 1.0 BG R 0.8 0.6 0.4 0.2 0 400 450 500 550 600 650 700 Wave Length [nm] – 11 – Relative Response
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ICX274AQ Image Sensor Characteristics (Ta = 25°C) Measurement Item Symbol Min. Typ. Max. Unit Remarks method G Sensitivity Sg 335 420 545 mV 1 1/30s accumulation R Rr 0.35 0.5 0.65 1 Sensitivity comparison B Rb 0.45 0.6 0.75 1 ∗2 Vsat 400 No line addition Saturation signal mV 2 Ta = 60°C ∗1 ∗3 Vsat2 400 2-line addition ∗4 –100 –92 Progressive scan mode ∗5 Smear Sm –94 –86 dB 3 2/4-line readout mode ∗6 –88 –80 2/8-line readout mode 20 Zone 0 and I % 4 Video signal shading SH 25 Zone 0 to II’ ∆ Sr
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ICX274AQ Zone Definition of Video Signal Shading 1628 (H) 4 4 8 V 10 H H 8 8 1236 (V) Zone 0, I 8 Zone II, II’ Ignored region V 10 Effective pixel region Measurement System ∗ CCD signal output [ A] ∗ CCD C.D.S AMP S/H Gr/Gb channel signal output [ B] ∗ S/H R/B channel signal output [ C] ∗ ∗ ∗ ∗ Note) Adjust the amplifier gain so that the gain between [ A] and [ B], and between [ A] and [ C] equals 1. Image Sensor Characteristics Measurement Method Color coding of this image sensor & Readout
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ICX274AQ Readout modes The diagrams below and on the following pages show the output methods for the following nine readout modes. Progressive scan mode 2/8-line readout mode 2/4-line readout mode 16 (V2C/V3C) G B 16 (V2C/V3C) G B 16 (V2C/V3C) G B 15 (V2C/V3C) R G 15 (V2C/V3C) R G 15 (V2C/V3C) R G 14 (V2A/V3A) G B 14 (V2A/V3A) G B 14 (V2A/V3A) G B 13 (V2B/V3B) R G 13 (V2B/V3B) R G 13 (V2B/V3B) R G 12 (V2C/V3C) G B 12 (V2C/V3C) G B 12 (V2C/V3C) G B 11 (V2C/V3C) R G 11 (V2C/V3C) R G 11 (V2C/V3
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ICX274AQ 2-line addition mode Center scan mode (1) Center scan mode (2) 16 (V2C/V3C) G B 16 (V2C/V3C) G B 16 (V2C/V3C) G B 15 (V2C/V3C) R G 15 (V2C/V3C) R G 15 (V2C/V3C) R G 14 (V2A/V3A) G B 14 (V2A/V3A) G B 14 (V2A/V3A) G B 13 (V2B/V3B) R G 13 (V2B/V3B) R G 13 (V2B/V3B) R G 12 (V2C/V3C) G B 12 (V2C/V3C) G B 12 (V2C/V3C) G B 11 (V2C/V3C) R G 11 (V2C/V3C) R G 11 (V2C/V3C) R G 10 (V2B/V3B) G B 10 (V2B/V3B) G B 10 (V2B/V3B) G B 9 (V2A/V3A) R G 9 (V2A/V3A) R G 9 (V2A/V3A) R G 8 (V2C/V3C) G B 8 (V2C/
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ICX274AQ Center scan mode (3) AF mode (1) AF mode (2) 16 (V2C/V3C) G B 16 (V2C/V3C) G B 16 (V2C/V3C) G B 15 (V2C/V3C) R G 15 (V2C/V3C) R G 15 (V2C/V3C) R G 14 (V2A/V3A) G B 14 (V2A/V3A) G B 14 (V2A/V3A) G B 13 (V2B/V3B) 13 (V2B/V3B) R G 13 (V2B/V3B) R G R G 12 (V2C/V3C) G B 12 (V2C/V3C) G B 12 (V2C/V3C) G B 11 (V2C/V3C) R G 11 (V2C/V3C) R G 11 (V2C/V3C) R G 10 (V2B/V3B) G B 10 (V2B/V3B) G B 10 (V2B/V3B) G B 9 (V2A/V3A) R G 9 (V2A/V3A) R G 9 (V2A/V3A) R G 8 (V2C/V3C) 8 (V2C/V3C) G B 8 (V2C/V3C) G
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ICX274AQ Center scan and AF modes Undesired portions (Swept by vertical register high-speed transfer) Picture center cut-out portion Description of Center Scan and AF Mode Operation The center scan and AF modes realize high frame rates by sweeping the top and bottom of the picture with high-speed transfer and cutting out the center of the picture. The various readout modes during center scan and AF operation are described below. AF modes AF mode (1), (2): The output method is the same as r
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ICX274AQ Measurement conditions (1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions, and the progressive scan readout mode is used. (2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb signal output or the R/B signal output of the measurement system. De
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ICX274AQ 4. Video signal shading Set to the standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjusting the luminous intensity so that the average value of the G channel signal output is 150mV. Then measure the maximum value (Gmax [mV]) and minimum value (Gmin [mV]) of the G signal output and substitute the values into the following formula. SH = (Gmax – Gmin)/150 × 100 [%] 5. Uniformity between video signal channels After measuring 4, measure the maximum (Rmax [mV]) and mini
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ICX274AQ – 20 – 15V Drive Circuit 100k 3.3V 1 20 0.1 2 19 XV3 3 18 4 17 XSG3C 5 16 0.1 CXD3400N XV2 6 15 0.1 7 14 XSG2C 8 13 9 12 0.1 10 11 –7.5V 0.1 1 20 1/35V XSUB 2 19 XV3 3 18 2SC4250 4 17 XSG3B CCD 1 2 3 4 5 6 7 8 9 10 OUT XSG3A 5 16 4.7k CXD3400N 0.1 XV2 6 15 ICX274 0.1 XSG2B 7 14 (BOTTOM VIEW) 3.3/20V XSG2A 8 13 0.01 XV4 9 12 20 19 18 17 16 15 14 13 12 11 XV1 10 11 Hφ1A VSUB Hφ2A 1M Hφ1B 2200p 3.3/16V Hφ2B 0.1 φRG 0.1 Substrate bias adjustment input voltage DCIN (VSUB in the circuit diagr
