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®
CY62146EV30 MoBL
4-Mbit (256K x 16) Static RAM
reduces power consumption by 80% when addresses are not
Features
toggling. The device can also be put into standby mode
• Very high speed: 45 ns
reducing power consumption by more than 99% when
• Wide voltage range: 2.20V–3.60V deselected (CE HIGH). The input and output pins (IO through
0
IO ) are placed in a high impedance state when:
15
• Pin compatible with CY62146DV30
• Deselected (CE HIGH)
• Ultra low standby power
• Outputs are disabled (OE
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® CY62146EV30 MoBL Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 6 256K x 16 A 5 IO –IO 0 7 A RAM Array 4 A 3 IO –IO 8 15 A 2 A 1 A 0 COLUMN DECODER BHE WE CE OE BLE [3, 4] Pin Configurations 44-pin TSOP II 48-ball VFBGA Top View Top View A A 1 44 4 5 126 3 4 5 A A 2 43 6 3 A A 3 42 7 2 A A OE A NC A BLE 0 2 1 A 4 OE 1 41 A 5 40 BHE 0 A A B 6 39 IO BHE CE IO CE BLE 3 4 8 0 IO 7 38 IO 0 15 IO 8 37 IO 1 14 A A C IO IO IO IO 5 6 9 10 1 2 IO 9 36 IO 2 13 IO 10 IO 35 3 12 V IO A V D A IO SS
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® CY62146EV30 MoBL [5, 6] DC Input Voltage ........... –0.3V to 3.9V (V + 0.3V) Maximum Ratings CC max Output Current into Outputs (LOW) ............................ 20 mA Exceeding the maximum ratings may impair the useful life of Static Discharge Voltage ......................................... >2001V the device. These user guidelines are not tested. (per MIL-STD-883, Method 3015) Storage Temperature ................................ –65°C to + 150°C Latch-up Current .........................
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® CY62146EV30 MoBL [9] Capacitance (For All Packages) Parameter Description Test Conditions Max Unit C Input Capacitance T = 25°C, f = 1 MHz, 10 pF IN A V = V CC CC(typ) C Output Capacitance 10 pF OUT [9] Thermal Resistance VFBGA TSOP II Parameter Description Test Conditions Package Package Unit Θ Thermal Resistance Still Air, soldered on a 3 × 4.5 inch, 75 77 °C/W JA (Junction to Ambient) two-layer printed circuit board Θ Thermal Resistance 10 13 °C/W JC (Junction to Case) AC Test Loads and W
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® CY62146EV30 MoBL [11, 12] Switching Characteristics (Over the Operating Range) 45 ns Parameter Description Min Max Unit Read Cycle t Read Cycle Time 45 ns RC t Address to Data Valid 45 ns AA t Data Hold from Address Change 10 ns OHA t 45 ns CE LOW to Data Valid ACE t 22 ns OE LOW to Data Valid DOE [13] t 5ns OE LOW to Low-Z LZOE [13, 14] t 18 ns OE HIGH to High-Z HZOE [13] t 10 ns CE LOW to Low-Z LZCE [13, 14] t 18 ns CE HIGH to High-Z HZCE t 0ns CE LOW to Power Up PU t 45 ns CE HIGH to Po
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® CY62146EV30 MoBL Switching Waveforms [16, 17] Read Cycle 1 (Address Transition Controlled) t RC ADDRESS t AA t OHA PREVIOUS DATA VALID DATA VALID DATA OUT [17, 18] Read Cycle No. 2 (OE Controlled) ADDRESS t RC CE t PD t t HZCE ACE OE t HZOE t DOE t LZOE BHE/BLE t HZBE t DBE t LZBE HIGH IMPEDANCE HIGHI MPEDANCE DATA VALID DATA OUT t LZCE t PU I CC V 50% 50% CC I SUPPLY SB CURRENT Notes: 16. The device is continuously selected. OE, CE = V , BHE and/or BLE = V . IL IL 17. WE is HIGH for read
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® CY62146EV30 MoBL Switching Waveforms (continued) [15, 19, 20] Write Cycle No. 1 (WE Controlled) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t BW BHE/BLE OE t HD t SD NOTE 21 DATA DATA IO IN t HZOE [15, 19, 20] Write Cycle No. 2 (CE Controlled) t WC ADDRESS t SCE CE t SA t t AW HA t PWE WE t BW BHE/BLE OE t t SD HD DATA DATA IO NOTE 21 IN t HZOE Notes: 19. Data IO is high impedance if OE = V . IH 20. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance stat
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® CY62146EV30 MoBL Switching Waveforms (continued) [20] Write Cycle No. 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE t BW BHE/BLE t t AW HA t t SA PWE WE t HD t SD DATA IO NOTE 21 DATA IN t LZWE t HZWE [20] Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) t WC ADDRESS CE t SCE t t AW HA t BW BHE/BLE t SA t PWE WE t HZWE t HD t SD NOTE 21 DATA DATA IO IN t LZWE Document #: 38-05567 Rev. *C Page 8 of 12
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® CY62146EV30 MoBL Truth Table CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High-Z Deselect/Power down Standby (I ) SB L X X H H High-Z Output Disabled Active (I ) CC L H L L L Data Out (IO –IO ) Read Active (I ) 0 15 CC L H L H L Data Out (IO –IO ); Read Active (I ) 0 7 CC IO –IO in High-Z 8 15 L H L L H Data Out (IO –IO ); Read Active (I ) 8 15 CC IO –IO in High-Z 0 7 L H H L L High-Z Output Disabled Active (I ) CC L H H H L High-Z Output Disabled Active (I ) CC L H H L H High-Z Outp
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® CY62146EV30 MoBL Package Diagrams Figure 1. 48-ball VFBGA (6 x 8 x 1 mm), 51-85150 BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2346 5 65 4 3 2 1 A A B B C C D D E E F F G G H H 1.875 A A 0.75 B 6.00±0.10 3.75 B 6.00±0.10 0.15(4X) SEATING PLANE C 51-85150-*D Document #: 38-05567 Rev. *C Page 10 of 12 0.25 C 8.00±0.10 0.26 MAX. 0.55 MAX. 0.21±0.05 1.00 MAX 0.10 C 8.00±0.10 5.25 0.75 2.625
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® CY62146EV30 MoBL Package Diagrams (continued) Figure 2. 44-pin TSOP II, 51-85087 51-85087-*A MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05567 Rev. *C Page 11 of 12 © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes n
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® CY62146EV30 MoBL Document History Page ® Document Title:CY62146EV30 MoBL , 4-Mbit (256K x 16) Static RAM Document Number: 38-05567 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 223225 See ECN AJU New Data Sheet *A 247373 See ECN SYT Changed Advance Information to Preliminary Moved Product Portfolio to Page 2 Changed V stabilization time in footnote #8 from 100 µs to 200 µs CC Removed Footnote #14(t ) from Previous revision LZBE Changed I from 2.0 µA to 2.5 µA CCDR Changed t
