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CY7C1516JV18, CY7C1527JV18
CY7C1518JV18, CY7C1520JV18
72-Mbit DDR-II SRAM 2-Word
Burst Architecture
Features Functional Description
■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36) The CY7C1516JV18, CY7C1527JV18, CY7C1518JV18, and
CY7C1520JV18 are 1.8V Synchronous Pipelined SRAM
■ 300 MHz clock for high bandwidth
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry and
■ 2-word burst for reducing address bus frequency
a 1-bit
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4M x 8 Array 4M x 9 Array 4M x 8 Array 4M x 9 Array CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Logic Block Diagram (CY7C1516JV18) Write Write 22 A Reg Reg (21:0) Address Register 8 LD K Output CLK R/W K Logic Gen. Control C DOFF Read Data Reg. C 16 CQ V 8 REF 8 Reg. Reg. CQ Control R/W Logic 8 NWS 8 [1:0] Reg. DQ 8 [7:0] Logic Block Diagram (CY7C1527JV18) Write Write 22 A Reg Reg (21:0) Address Register 9 LD K Output CLK R/W K Logic Gen. Control C DOFF Read Data Reg. C 18 CQ V 9 REF 9
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1M x 36 Array 2M x 18 Array 1M x 36 Array 2M x 18 Array CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Logic Block Diagram (CY7C1518JV18) Burst A0 Logic Write Write 22 21 A Reg Reg (21:0) A Address (21:1) Register 18 LD K Output CLK R/W K Logic Gen. Control C DOFF Read Data Reg. C 36 CQ V 18 REF 18 Reg. Reg. Control CQ R/W Logic 18 18 BWS DQ [1:0] Reg. 18 [17:0] Logic Block Diagram (CY7C1520JV18) Burst A0 Logic Write Write 21 20 A Reg Reg (20:0) A Address (20:1) Register 36 LD K Output CL
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Pin Configuration [1] The pin configuration for CY7C1516JV18, CY7C1527JV18, CY7C1518JV18, and CY7C1520JV18 follow. 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1516JV18 (8M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ AA R/W NWS K NC/144M LD AA CQ 1 B NC NC NC A NC/288M K NWS ANC NC DQ3 0 C NC NC NC V AAA V NC NC NC SS SS D NC NC NC V V V V V NC NC NC SS SS SS SS SS E NC NC DQ4 V V V V V NC NC DQ2 DDQ SS SS SS DDQ F NC NC NC V V V V V NC NC NC DDQ DD S
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Pin Configuration [1] The pin configuration for CY7C1516JV18, CY7C1527JV18, CY7C1518JV18, and CY7C1520JV18 follow. (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1518JV18 (4M x 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ AA R/W BWS K NC/144M LD AA CQ 1 B NC DQ9 NC A NC/288M K BWS ANC NC DQ8 0 C NC NC NC V AA0A V NC DQ7 NC SS SS D NC NC DQ10 V V V V V NC NC NC SS SS SS SS SS E NC NC DQ11 V V V V V NC NC DQ6 DDQ SS SS SS DDQ F NC DQ12 NC V V V
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Pin Definitions Pin Name IO Pin Description DQ Input Output- Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write [x:0] Synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is driven out on the rising edge of both the C and C clocks during read operations or K and K when in single clock mode. When read access is deselected, Q are auto
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Pin Definitions (continued) Pin Name IO Pin Description CQ Output Clock CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing for the echo clocks is shown in the AC Timing table. CQ Output Clock CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 presented to the burst counter. The burst counter increments the Functional Overview address in a linear fashion. On the following K clock rise, the data The CY7C1516JV18, CY7C1527JV18, CY7C1518JV18, and presented to D is latched and stored into the 18-bit write [17:0] CY7C1520JV18 are synchronous pipelined Burst SRAMs are both asserted active. On the data register, provided BWS [1:0] equipped with a DDR interface, which operates with a read
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Depth Expansion is referenced DDR-II. CQ is referenced with respect to C and CQ with respect to C. These are free-running clocks and are control signal for Depth expansion requires replicating the LD synchronized to the output clock of the DDR-II. In single clock each bank. All other control signals can be common between is generated mode, CQ is generated with respect to K and CQ banks as appropriate. with respect to K. The timing for the e
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Truth Table [2, 3, 4, 5, 6, 7] The truth table for the CY7C1516JV18, CY7C1527JV18, CY7C1518JV18, and CY7C1520JV18 follows. Operation K LD R/W DQ DQ Write Cycle: L-H L L D(A1) at K(t + 1) ↑ D(A2) at K(t + 1) ↑ Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: L-H L H Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2) ↑ Load address; wait one and a half cycle; read data on consecutive C and C rising edges. NOP
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Write Cycle Descriptions [2, 8] The write cycle description table for CY7C1527JV18 follows. BWS K K Comments 0 L L–H – During the data portion of a write sequence, the single byte (D ) is written into the device. [8:0] ) is written into the device. L – L–H During the data portion of a write sequence, the single byte (D [8:0] H L–H – No data is written into the device during this portion of a write operation. H – L–H No data is written into t
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Instruction Register IEEE 1149.1 Serial Boundary Scan (JTAG) Three-bit instructions can be serially loaded into the instruction These SRAMs incorporate a serial boundary scan Test Access register. This register is loaded when it is placed between the TDI Port (TAP) in the FBGA package. This part is fully compliant with and TDO pins, as shown in TAP Controller Block Diagram on IEEE Standard #1149.1-2001. The TAP operates using JEDEC page 15. U
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 IDCODE PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection The IDCODE instruction loads a vendor-specific, 32-bit code into of another boundary scan test operation. the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the The shifting of data for the SAMPLE and PRELOAD phases can device when the TA
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 TAP Controller State Diagram [9] The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 0 SHIFT-DR SHIFT-IR 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 0 Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-12559 Rev
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 TAP Controller Block Diagram 0 Bypass Register 2 1 0 Selection Selection TDI TDO Instruction Register Circuitry Circuitry 31 30 29 . . 2 1 0 Identification Register . 108 . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics [10, 11, 12] Over the Operating Range Parameter Description Test Conditions Min Max Unit V Output HIGH Voltage I = −2.0 mA 1.4 V OH1 OH Output HIGH Voltage I = −100 μA1.6 V V OH2 OH
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 TAP AC Switching Characteristics [13, 14] Over the Operating Range Parameter Description Min Max Unit t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH 20 ns TH t TCK Clock LOW 20 ns TL Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hold Times t TMS Hold after TCK Clock Rise 5 ns TMSH t TDI Hold after Clock Rise 5 ns TDIH t Capt
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Identification Register Definitions Value Instruction Field Description CY7C1516JV18 CY7C1527JV18 CY7C1518JV18 CY7C1520JV18 Revision Number 000 000 000 000 Version number. (31:29) Cypress Device ID 11010100010000100 11010100010001100 11010100010010100 11010100010100100 Defines the type of (28:12) SRAM. Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Allows unique (11:1) identification of SRAM vendor. ID Register 1111 Indi
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P29 9G 57 5B85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N32 9F 60 5C88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43
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~ ~ CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 DLL Constraints Power Up Sequence in DDR-II SRAM ■ DLL uses K clock as its synchronizing input. The input must DDR-II SRAMs must be powered up and initialized in a have low phase jitter, which is specified as t . KC Var predefined manner to prevent undefined operations. ■ The DLL functions at frequencies down to 120 MHz. Power Up Sequence ■ If the input clock is unstable and the DLL is enabled, then the ■ Apply power and drive DOFF eith
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Current into Outputs (LOW) ........................................ 20 mA Maximum Ratings Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V Exceeding maximum ratings may impair the useful life of the Latch Up Current .................................................... >200 mA device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Pow
