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SERVICE MANUAL FOR
SERVICE MANUAL FOR
SERVICE MANUAL FOR
8050QMA
8050QMA
8050QMA
BY: ZX Xiao
Repair Technology Research Department /EDVD Repair Technology Research Department /EDVD
Jun.2005 / R01
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8050QMA N/B Maintenance 8050QMA N/B Maintenance Contents 1. Hardware Engineering Specification ……………………………………………………………………… 4 1.1 Introduction ……………………………………………………………………………………………………………….. 4 1.2 System Hardware Parts …………………………………………………………………………………………………... 7 1.3 Other Functions …………………………………………………………………………………………………………… 32 1.4 Power Management ………………………………………………………………………………………………………. 39 1.5 Appendix 1 : Intel ICH6-M GPIO Definitions …………………………………………………………………………. 42 1.6 Appendix 2 : W83L950
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8050QMA N/B Maintenance 8050QMA N/B Maintenance Contents 5. Pin Description of Major Component …….………………………………………………………………. 78 5.1 Intel 915PM North Bridge ………………………………………………………………………………………………. 78 5.2 Intel ICH6-M South Bridge ……………………………………………………………………………………………… 88 6. System Block Diagram ……………………………………………………………………………………… 98 7. Maintenance Diagnostics …………………………………………………………………………………… 99 7.1 Introduction ……………………………………………………………………………………………………………….. 99 7.2 Maintenance Diagnostics…………………………………
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8050QMA N/B Maintenance 8050QMA N/B Maintenance Contents 8.12 PC Card Socket Failure ………………………………………………………………………………………………… 134 9. Spare Parts List ……………………………………………………………………………………………... 136 10. Reference Material …...……………………………………………………………………………………. 150 3 MiTac Secret Confidential Document
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8050QMA N/B Maintenance 8050QMA N/B Maintenance 1. Hardware Engineering Specification 1.1 Introduction 1.1.1 General Description This document describes the brief introduction for MiTAC 8050QMA portable notebook computer system. 1.1.2 System Overview The MiTAC 8050Q model is designed for Intel Dothan processor with 533MHz FSB with Micro-FCPGA package. This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has standard hardware peripheral interface.
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8050QMA N/B Maintenance 8050QMA N/B Maintenance (DMI) connecting with Intel ICH6-M. The Intel ICH6-M integrates three Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the Audio Controller with AC97 interface, the Ethernet includes a 32-bit PCI controller, the IDE Master/Slave controllers, the SATA controller and Direct Media Interface technology. The Realtek RTL8100CL is a highly integrated, cost-effective single-chip Fast Ethernet controller that provides 32- bit performance, PCI
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8050QMA N/B Maintenance 8050QMA N/B Maintenance configurations, so that compact, high performance systems can be implemented easily. A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME, Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus mastering IDE, Plug and Play, Advanced Power Management (APM) with application restart, software-controlled power shutdown. Following chapters wil
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8050QMA N/B Maintenance 8050QMA N/B Maintenance 1.2 System Hardware Parts Intel® Pentium® M Processor (Dothan) 90nm, 2M L2, 533 MHz FSB CPU Intel® Celeron® M processor, 90nm, 512K L2, 400 MHz FSB Core logic Intel 915PM + ICH6-M chipset System BIOS SST49LF004A 0MB DDR2-SDRAM on Board Expandable with combination of optional 128MB/256MB/512MB/1GB(P) memory Memory Two 200-pin DDR2 400/533 SDRAM Memory Module Type I MXM Interface (max 25W) with 8 cells Vram VGA Control Priority at launch
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8050QMA N/B Maintenance 8050QMA N/B Maintenance 1.2.1 Intel Dothan Processors in Micro-FCBGA Package Intel Dothan Processors with 479 pins Micro-FCBGA package. It will be manufactured on Intel’s advanced 90 nanometer process technology with copper interconnect. It’s features include Intel Architecture with Dynamic Execution, On-die primary 32-kB instruction cache and 32-kB write-back data cache, on-die 2-MB second level cache with advanced Transfer Cache Architecture, Data Prefetch Logic, St
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8050QMA N/B Maintenance 8050QMA N/B Maintenance Supports tight ppm accuracy clocks for Serial-ATA and SRC. Supports spread spectrum modulation, 0 to –0.5% down spread. Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning. Supports undriven differential CPU, SRC pair in PD# for power management. 1.2.3 The Mobile Intel 915PM Express Chipset The Mobile Intel 915PM Express Chipset integras a memory controller hub (MCH) designed for use with the Doth
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8050QMA N/B Maintenance 8050QMA N/B Maintenance ® Intel Dothan processor AGTL+ bus driver technology with integrated GTL termination resistors (gated AGTL+ receivers for reduced power) Supports 32-bit AGTL+ host bus addressing Supports system bus at 533MT/s (533 MHz) and 400MT/s (400 MHz) 2X Address, 4X data Host bus dynamic bus inversion HDINV support 12 deep, in-order queue Memory System Directly supports to two DDR or DDR2 SDRAM channels, 64-bts wide. Supports SO-DIMMs of
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8050QMA N/B Maintenance 8050QMA N/B Maintenance 256-MB, 512-MB and 1-GB technology using x8 and x16 devices. Three memory channel organizations are supported for DDR / DDR2 : – Single channel – Dual channel interleaved – Dual channel asymmetric Supports DDR 333 devices and DDR2 400 /533 devices – Supports on-die termination (ODT) for DDR2 Supports Fast Chip Select mode Supports partial write to memory using Data Mask signal (DM) Supports high-density memory package for DDR or DDR2 ty
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8050QMA N/B Maintenance 8050QMA N/B Maintenance Supports only 1.5-V AGP electrics 32 deep AGP request queue Hierarchical PCI-compliant configuration mechanism for downstream devices Direct Media Interface (DMI) – Chip-to-chip interconnect between the GMCH and ICH6-M – DMI x2 and DMI x4 configuration supported – Bit swapping is supported – Lane reversal is not supported 1.2.4 I/O Controller Hub : Intel ICH6-M The ICH6 provides extensive I/O support. Functions and capabilities includ
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8050QMA N/B Maintenance 8050QMA N/B Maintenance Integrated Serial ATA host controller with independent DMA operation on two ports and AHCI support Integrated IDE controller supports Ultra ATA100/66/33 USB host interface with support for three USB ports; three UHCI host controllers; one EHCI high-speed USB2.0 Host controller Integrated LAN controller 2 System Management Bus (SMBus) Specification, Version 2.0 with additional support for I C devices Supports Audio Codec ’97, Revision 2
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8050QMA N/B Maintenance 8050QMA N/B Maintenance Pin out Compatible with CB1410 PCI Interface – Compliant with PCI Local Bus Specification Revision 2.3 – Compliant with PCI Bus Power Management Interface Specification Revision 1.1 – Compliant with PCI Mobile Design Guide Version 1.1 – Compliant with Advanced Configuration and Power Interface Specification Revision 1.0 CardBus Interface – Compliant with PC Card Standard 8.0 – Support Standardized Zoomed Video Register Model – Support SPKROUT C
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8050QMA N/B Maintenance 8050QMA N/B Maintenance Memory Stick Interface – Compliant with Memory Stick PRO Format Specification Version 1.0 – Support 4-bit Parallel Data Transfer Mode – Memory Stick Clock Frequency Up to 40Mhz – Support DMA Mode to Minimize CPU Overhead – Support Traffic LED Light – Support Over Current Protection Interrupt Configuration – Support Parallel PCI Interrupts – Support Parallel IRQ and Parallel PCI Interrupts – Support Serialized IRQ and Parallel PCI Interrupts
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8050QMA N/B Maintenance 8050QMA N/B Maintenance Support parallel 4-wire power switch interface 1.2.6 AC’97 Audio System: Advance Logic, Inc, ALC655 The ALC655 is a 16-bit, full duplex AC'97 2.3 compatible six channels audio CODEC designed for PC multimedia systems, including host/soft audio and AMR/CNR based designs. The ALC655 incorporates proprietary converter technology to meet performance requirements on PC99/2001 systems. The ALC655 CODEC provides three pairs of stereo outputs with 5
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8050QMA N/B Maintenance 8050QMA N/B Maintenance Meets performance requirements for audio on PC99/2001 systems Meets Microsoft WHQL/WLP 2.0 audio requirements 16-bit Stereo full-duplex CODEC with 48KHz sampling rate Compliant with AC’97 2.3 specifications – 14.318MHz- 24.576MHz PLL to save crystal – 12.288MHz BITCLK input can be consumed – Integrated PCBEEP generator to save buzzer – Interrupt capability Three analog line-level stereo inputs with 5-bit volume control: LINE_IN, CD, AUX
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8050QMA N/B Maintenance 8050QMA N/B Maintenance Stereo MIC record for AEC/BF application Supports Power Off CD function Adjustable VREFOUT control Supports double sampling rate (96KHz) of DVD audio playback Support 48KHz of S/PDIF output is compliant with AC’97 rev2.3 specification Power support: Digital: 3.3V; Analog: 3.3V/5V 1.2.7 MDC: Pctel Modem Daughter Card PCT2303W (Askey V1456VQL-P1) The PCT2303W chipset is designed to meet the demand of this emerging worldwide AMR/MDC market
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8050QMA N/B Maintenance 8050QMA N/B Maintenance small outline packages (AC’97 interface on PCT303A and phone-line interface on PCT303W). The chip set eliminates the need for an AFE, an isolation transformer, relays, opto-isolators, and 2-to 4-wire hybrid. The PCT2303W chip set dramatically reduces the number of discrete components and cost required to achieve compliance with international regulatory requirements. The PCT2303W complies with AC’97 Interface specification Rev. 2.1. The chip set
