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Application Note: Virtex-4 Series
High-Performance DDR2 SDRAM
R
Interface Data Capture Using ISERDES
and OSERDES
XAPP721 (v1.3) February 2, 2006
Author: Maria George
Summary This application note describes a data capture technique for a high-performance DDR2
SDRAM interface. This technique uses the Input Serializer/Deserializer (ISERDES) and Output
Serializer/Deserializer (OSERDES) features available in every Virtex™-4 I/O. This technique
can be used for memory interfaces with frequencies of
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R Write Datapath DCM PMCD#1 CLKfast Input CLKfast_0 CLKIN CLK0 CLKA CLKA1 System Reset* * CLKdiv_0 RST CLK90 RST CLKA1D2 CLKFB LOCKED CLKFB PMCD#2 CLKfast_90 CLKA CLKA1 CLKB CLKdiv_90 * RST CLKA1D2 CLKFB x702_04_051105 Figure 1: Clocking Scheme for the High-Performance Memory Interface Design CLKdiv_0 CLKfast_0 Memory Device Clock Command WRITE IDLE Control (CS_L) X721_02_080205 Figure 2: Command and Control Timing Write Datapath The write datapath uses the built-in OSERDES availabl
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R Write Datapath D1 DQ D2 Write Data Words 0-3 D3 D4 OSERDES CLKDIV CLK CLKdiv_90 CLKfast_90 TM IOB ChipSync Circuit X721_03_080305 Figure 3: Write Data Transmitted Using OSERDES CLKfast_0 CLKfast_90 Clock Forwarded to Memory Device Command WRITE IDLE Control (CS_L) Strobe (DQS) Data (DQ), OSERDES Output D0 D1 D2 D3 X721_04_120505 Figure 4: Write Strobe (DQS) and Data (DQ) Timing for a Write Latency of Four March 2006 Memory Interfaces Solution Guide 57
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R Write Datapath Write Timing Analysis Table 1 shows the write timing analysis for an interface at 333 MHz (667 Mb/s). Table 1: Write Timing Analysis at 333 MHz Uncertainties Uncertainties Uncertainty Parameters Value Meaning before DQS after DQS T 3000 Clock period. CLOCK T 150 150 150 Duty-cycle distortion from memory DLL is MEMORY_DLL_DUTY_CYCLE_DIST subtracted from clock phase (equal to half the clock period) to determine T DATA_PERIOD. T 1350 Data period is half the clock period with 10
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R Write Datapath Controller to Write Datapath Interface Table 2 lists the signals required from the controller to the write datapath. Table 2: Controller to Write Datapath Signals Signal Signal Name Signal Description Notes Width ctrl_WrEn 1 Output from the controller to the write Asserted for two CLKDIV_0 cycles for a burst length datapath. of 4 and three CLKDIV_0 cycles for a burst length of 8. Write DQS and DQ generation begins when this signal is asserted. Asserted one CLKDIV_0 cycle earli
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R Write Datapath CLKdiv_0 Clock Forwarded to Memory Device CLKdiv_90 CLKfast_90 Command WRITE IDLE Control (CS_L) ctrl_WrEn ctrl_wr_disable User Interface Data D0,D1,D2,D3 FIFO Out OSERDES Inputs D1, D2, D3, D4 X,X,D0,D1 D2,D3,X,X OSERDES Inputs T1, T2, T3, T4 1,1,0,0 0,0,1,1 Strobe (DQS) Data (DQ), OSERDES Output D0 D1 D2 D3 X721_05_080205 Figure 5: Write DQ Generation with a Write Latency of 4 and a Burst Length of 4 CLKdiv_0 CLKfast_0 Clock Forwarded to Memory Device CLKdiv_180 Command WRITE
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R Read Datapath Read Datapath The read datapath comprises the read data capture and recapture stages. Both stages are implemented in the built-in ISERDES available in every Virtex-4 I/O. The ISERDES has three clock inputs: CLK, OCLK, and CLKDIV. The read data is captured in the CLK (DQS) domain, recaptured in the OCLK (FPGA fast clock) domain, and finally transferred to the CLKDIV (FPGA divided clock) domain to provide parallel data. CLK: The read DQS routed using BUFIO provides the CLK inp
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R Read Datapath Table 3 shows the read timing analysis at 333 MHz required to determine the delay required on DQ bits for centering DQS in the data valid window. Table 3: Read Timing Analysis at 333 MHz Parameter Value (ps) Meaning T 3000 Clock period. CLOCK T 1500 Clock phase for DDR data. PHASE T 350 Sample Window from Virtex-4 data sheet for SAMP_BUFIO a -12 device. It includes setup and hold for an IOB FF, clock jitter, and 150 ps of tap uncertainty. T 100 BUFIO clock resource duty-cycle d
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R Read Datapath Figure 8 shows the timing waveform for read data and strobe delay determination. The waveforms on the left show a case where the DQS is delayed due to BUFIO and clocking resource, and the ISERDES outputs do not match the expected data pattern. The waveforms on the right show a case where the DQS and DQ are delayed until the ISERDES outputs match the expected data pattern. The lower end of the frequency range useful in this design is limited by the number of available taps in t
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R Read Datapath Controller to Read Datapath Interface Table 4 lists the control signals between the controller and the read datapath. Table 4: Signals between Controller and Read Datapath Signal Signal Name Signal Description Notes Width ctrl_Dummyread_Start 1 Output from the controller to the This signal must be asserted when valid read data read datapath. When this signal is available on the data bus. is asserted, the strobe and data This signal is deasserted when the calibration begin. dp_d
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R Reference Design The ctrl_RdEn signal is required to validate read data because the DDR2 SDRAM devices do not provide a read valid or read-enable signal along with read data. The controller generates this read-enable signal based on the CAS latency and the burst length. This read-enable signal is input to an SRL16 (LUT-based shift register). The number of register stages required to align the read-enable signal to the ISERDES read data output is determined during calibration. One read-enable
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R Reference Design Utilization Reference Table 5 lists the resource utilization for a 64-bit interface including the physical layer, the controller, the user interface, and a synthesizable test bench. Design Table 5: Resource Utilization for a 64-Bit Interface Utilization Resources Utilization Notes Slices 5861 Includes the controller, synthesizable test bench, and the user interface. BUFGs 6 Includes one BUFG for the 200 MHz reference clock for the IDELAY block. BUFIOs 8 Equals the number
