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S1D13705 Embedded Memory LCD Controller
S1D13705
TECHNICAL MANUAL
Document No. X27A-Q-001-04
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current.
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Epson Research and Development Page 3 Vancouver Design Center Customer Support Information Comprehensive Support Tools Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of graphics systems. Evaluation / Demonstration Board • Assembled and fully tested graphics evaluation board with installation guide and sche- matics. To borrow an evaluation board, please contact your local Seiko Epson Corp. sales repre- s
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ENERGY SAVING EPSON GRAPHICS S1D13705 February 2001 S1D13705 Embedded Memory LCD Controller The S1D13705 is a color/monochrome LCD graphics controller with an embedded 80K Byte SRAM display buffer. The high integration of the S1D13705 provides a low cost, low power, single chip solution to meet the requirements of embedded markets such as Office Automation equipment, Mobile Commu- nications devices, and Palm-size PCs where board size and battery life are major concerns. Products requiring a “P
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GRAPHICS S1D13705 ■ DESCRIPTION Memory Interface Display Modes Embedded 80K byte SRAM display buffer. 1/2/4/8 bit-per-pixel (bpp) support on LCD. Up to 16 shades of gray using FRM on CPU Interface monochrome passive LCD panels. Direct support for: Up to 256 simultaneous colors from a possible 4096 Hitachi SH-3. colors on passive STN and active matrix TFT/D-TFD Hitachi SH-4. LCD panels. Motorola M68xxx. MPU bus interface with programmable READY. Split Screen Display: allows two d
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S1D13705 Embedded Memory LCD Controller Hardware Functional Specification Document Number: X27A-A-001-10 Copyright © 1999, 2002 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are ac
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Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Page 4 Epson Research and Development Vancouver Design Center 7.1.5 Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.1.6 Generic #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .34 7.3 Display Interface . . . . . . .
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Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 5-1: Summary of Power On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 5-2: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 5-3: LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 6-1: Absolute Max
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Epson Research and Development Page 7 Vancouver Design Center List of Figures Figure 3-1: Typical System Diagram (SH-4 Bus). . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Figure 3-2: Typical System Diagram (SH-3 Bus). . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Figure 3-3: Typical System Diagram (M68K #1 Bus) . . . . . . . . . . . . . . . . . . . . . . . . .13 Figure 3-4: Typical System Diagram (
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Page 8 Epson Research and Development Vancouver Design Center Figure 11-2: 2 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . .71 Figure 11-3: 4 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . .72 Figure 11-4: 1 Bit-per-pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . .73 Figure 11-5: 2 Bit-per-pixel Color Mode Data Output Path . . . . .
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Epson Research and Development Page 9 Vancouver Design Center 1 Introduction 1.1 Scope This is the Hardware Functional Specification for the S1D13705 Embedded Memory LCD Controller Chip. Included in this document are timing diagrams, AC and DC character- istics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. This document is updated as appropriate. Please check for the latest revision
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Page 10 Epson Research and Development Vancouver Design Center 2 Features 2.1 Integrated Frame Buffer Embedded 80K byte SRAM display buffer. 2.2 CPU Interface Direct support of the following interfaces: Hitachi SH-3. Hitachi SH-4. Motorola M68K. MPU bus interface using WAIT# signal. Direct memory mapping of internal registers. Single level CPU write buffer. Registers are mapped into upper 32 bytes of 128K byte address space. The complete 80K byte display buffer is directly and con
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Epson Research and Development Page 11 Vancouver Design Center 2.4 Display Modes SwivelView™: direct 90° hardware rotation of display image for portrait mode display 1/2/4 bit-per-pixel (bpp), 2/4/16-level grayscale display. 1/2/4/8 bit-per-pixel, 2/4/16/256-level color display. Up to 16 shades of gray by FRM on monochrome passive LCD panels; a 256x4 Look- Up Table is used to map 1/2/4 bpp modes into these shades. 256 simultaneous of 4096 colors on color passive and active matrix LCD
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Page 12 Epson Research and Development Vancouver Design Center 3 Typical System Implementation Diagrams . Oscillator SH-4 BUS CSn# CS# A[16:0] AB[16:0] D[15:0] DB[15:0] FPDAT[7:0] D[7:0] FPSHIFT FPSHIFT WE1# WE1# BS# 8-bit BS# S1D13705 FPFRAME FPFRAME RD/WR# RD/WR# LCD FPLINE FPLINE RD# RD# Display DRDY MOD WE0# WE0# RDY# WAIT# LCDPWR CKIO BCLK RESET# RESET# Figure 3-1: Typical System Diagram (SH-4 Bus) . Oscillator SH-3 BUS CSn# CS# A[16:0] AB[16:0] D[15:0] DB[15:0] FPDAT[7:4] D[3:0] FPSHIFT F
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Epson Research and Development Page 13 Vancouver Design Center . Oscillator MC68000 BUS A[23:17] CS# Decoder FC0, FC1, FC2 A[16:1] AB[16:1] D[15:0] DB[15:0] FPDAT[7:4] D[3:0] FPSHIFT FPSHIFT LDS# 4-bit AB0 S1D13705 FPFRAME FPFRAME UDS# WE1# LCD FPLINE FPLINE AS# BS# Display DRDY MOD R/W# RD/WR# DTACK# WAIT# LCDPWR CLK BCLK RESET# RESET# Figure 3-3: Typical System Diagram (M68K #1 Bus) . Oscillator MC68030 BUS A[31:17] CS# Decoder FC0, FC1, FC2 A[16:0] AB[16:0] D[31:16] DB[15:0] FPDAT[7:0] D[7:0]
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Page 14 Epson Research and Development Vancouver Design Center . Oscillator BS# GENERIC #1 BUS CSn# CS# A[16:0] AB[16:0] D[15:0] DB[15:0] FPDAT[11:0] D[11:0] FPSHIFT FPSHIFT 12-bit WE0# S1D13705 WE0# FPFRAME FPFRAME TFT WE1# WE1# FPLINE FPLINE Display RD RD0# DRDY DRDY RD1# RD/WR# WAIT# WAIT# LCDPWR BCLK BCLK RESET# RESET# Figure 3-5: Typical System Diagram (Generic #1 Bus) . Oscillator BS# ISA REFRESH Decoder CS# BUS SA[19:17] SA[16:0] AB[16:0] SD[15:0] DB[15:0] FPDAT[8:0] D[8:0] SMEMW# WE0# FP
