ページ1に含まれる内容の要旨
Data Book
32bit Micro controller
TLCS-900/H1 series
TMP92CZ26AXBG
TENTATIVE
It’s first version technical data sheet.
Since this revision 0.2 is still under working, there may
be some mistakes in it.
When you will start to design, please order the latest
one.
Rev0.2 09/Dec./2005
ページ2に含まれる内容の要旨
Table of Contents TLCS-900/H1 Devices TMP92CZ26A 1. Outline and Features 92CZ26A-1 2. Pin Assignment and Pin Functions 92CZ26A-6 2.1 Pin Assignment Diagram 92CZ26A-6 2.2 Pin names and Functions 92CZ26A-8 3. Operation 92CZ26A-14 3.1 CPU 92CZ26A-14 3.2 Memory Map 92CZ26A-19 3.3 Clock Function and Standby Function 92CZ26A-20 3.4 Boot ROM 92CZ26A-43 3.5 Int
ページ3に含まれる内容の要旨
3.12 8 bit timers (TMRA) 92CZ26A-266 3.13 16 bit timer (TMRB) 92CZ26A-294 3.14 Serial channel (SIO) 92CZ26A-315 3.15 Serial Bus Interface (SBI) 92CZ26A-344 3.16 USB controller 92CZ26A-366 3.17 SPIC (SPI controller) 92CZ26A-477 3.18 I2S 92CZ26A-496 3.19 LCD controller (LCDC) 92CZ26A-508 3.20 Touch screen interface (TSI) 92CZ26A-564 3.21 Real time clock (RTC)
ページ4に含まれる内容の要旨
TMP92CZ26A CMOS 32-Bit Micro controllers TMP92CZ26AXBG 1. Outline and Features TMP92CZ26A is high-speed advanced 32-bit micro-controller developed for controlling equipment which processes mass data. TMP92CZ26AXBG is housed in a 228-pin BGA package. (1) CPU : 32-bit CPU(High-speed 900/H1 CPU) • Compatible with TLCS-900/L1 instruction code • 16Mbytes of linear address space • General-purpose register and register banks • Micro DMA : 8channels (62.5ns/4 bytes at fSYS = 80MHz, b
ページ5に含まれる内容の要旨
TMP92CZ26A (4) External memory expansion • Expandable up to 3.1G bytes (shared program/data area) • Can simultaneously support 8/16-bit width external data bus Dynamic data bus sizing • Separate bus system (5) Memory controller • Chip select output : 4 channel • One channel in 4 channels is enabled detailed AC enable setting (6) 8-bit timers : 8 channels (7) 16-bit timer/event counter : 2 channel (8) General-purpose serial interface : 1 channels • UART/synchronous mode
ページ6に含まれる内容の要旨
TMP92CZ26A (17) Touch screen interface • Built-in Switch of Low-resistor, and available to delete external components for shift change row/column (18) Watch dog timer (19) Melody/alarm generator • Melody: Output of clock 4 to 5461Hz • Alarm: Output of the 8 kinds of alarm pattern • 5 kinds of interval interrupt (20) MMU • Expandable up to 3.1G bytes (3 local area/8 bank method) • Independent bank for each Program, Read-data, Write-data, Source and Destination of DMAC (Odd channe
ページ7に含まれる内容の要旨
TMP92CZ26A (28) Stand-by function • Three Halt modes : IDLE2 (programmable), IDLE1, STOP • Each pin status programmable for stand-by mode • Built-in power supply management circuits (PMC) for leak current provision (29) Clock controller • Built-in two blocks of clock doubler (PLL). PLL supplies 48 MHz for USB and 80 MHz for CPU from 10MHz • Clock gear function: Selectable high-frequency clock fc to fc/16 • Clock for Timer (fs = 32.768 kHz) (30) Operating voltage: • Internal V = 1.5
ページ8に含まれる内容の要旨
TMP92CZ26A DVCC3A [12] (AN0 to AN1)PG0 to PG1 DVCC3B [1] 10-bit 6ch (AN2, MX)PG2 DVCC1A [5] 900/H1 CPU AD (AN3, MY, ADTRG )PG3 DVCC1B [1] Converter DVSSCOM (AN4 to AN5)PG4 to PG5 AVCC, AVSS DVCC1C [1] PLL DVSS1C [1] VREFH, VREFL XWA W A X1 H-OSC Touch Screen X2 (PX, INT4)P96 XBC B C I/F Clock gear (PY)P97 (TSI) D E XDE XT1 L-OSC (TXD0)P90 XHL H L XT2 SERIAL I/O (RXD0)P91 RESET SIO0 XIX IX (CTS0, SCLK 0)P92 DBGE AM [1:0] (I2S0CKO)PF 0 2 XIY IY
ページ9に含まれる内容の要旨
TMP92CZ26A 2. Pin Assignment and Pin Functions The assignment of input/output pins for TMP92CZ26A, their names and functions are as follows; 2.1 Pin Assignment Diagram (Top View) Figure 2.1.1 shows the pin assignment of the TMP92CZ26A. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12A13A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12B13B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12C13C14 C15 C16 C17 D1 D2 D3 D5 D6 D7 D8 D9 D10 D11 D12D13 D15 D16 D17 E1 E2 E3 E4 E14 E
ページ10に含まれる内容の要旨
TMP92CZ26A Table 2.1.1 Pin number and the name Ball Ball Ball Ball Pin name Pin name Pin name Pin name No. No. No. No. A1 Dummy1 D9 P73,EA24 J15 PT5,LD13 P15 PK4,LHSYNC A2 PG2,AN2, MX D10 PF4,I2S1DO J16P47,A7 P16 P13,D11 A3 PA6,KI6 D11 PF7,SDCLK J17 P46,A6 P17 P14,D12 A4 PA5,KI5 D12 PJ4,SDLUDQM K1 PN3,KO3 R1 X2 A5 PA3,KI3 D13 P85, K2PN4,KO4 R2 PC7,KO8 CSZC A6 PA1,KI1 D15 PU6,LD22 K3 PN5,KO5 R3 PC3,INT3,TA2IN A7 DVCC1A5 D16 P61,A17 K4 PN6,KO6 R4 PX5,X1USB A8 PF1,I2S0DO D17 P60,A16 K
ページ11に含まれる内容の要旨
TMP92CZ26A 2.2 Pin names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 Pin names and functions (1/6) Number of Pin name I/O Functions Pins D0 to D7 8 I/O Data: Data bus D0 to D7. P10 to P17 I/O Port 1: I/O port. Input or output is specifiable in units of bit. 8 D8 to D15 I/O Data : Data bus D8 to D15. P40 to P47 Output Port 4: Output port. 8 A0 to A7 Output Address : Address bus A0 to A7. P50 to P57 Output Port 5: Output por
ページ12に含まれる内容の要旨
TMP92CZ26A Table 2.2.1 Pin names and functions (2/6) Number Pin name I/O Functions of Pins P86 Output Port 86 : Output port. CSZD 1 Output Expanded address ZD : Outputs “Low” when address is within specified address area. ND0CE Output Chip select of NAND Flash 0: Outputs “Low” when NAND Flash 0 is enable. P87 Output Port 87 : Output port. CSXB 1 Output Expanded address XB : Outputs “Low” when address is within specified address area. ND1CE Output Chip select of NAND Flash 1:
ページ13に含まれる内容の要旨
TMP92CZ26A Table 2.2.1 Pin names and functions (3/6) Number of Pin name I/O Functions Pins PF0 I/O Port F0: I/O port. 1 I2S0CKO Output Outputs clock of I2S0. PF1 I/O Port F1: I/O port. 1 I2S0DO Output Outputs data of I2S0. PF2 I/O Port F2: I/O port. 1 I2S0WS Output Outputs word select signal of I2S0. PF3 I/O Port F3: I/O port. 1 I2S0WS Output Outputs clock of I2S1. PF4 I/O Port F4: I/O port. 1 I2S1CKO Output Outputs data of I2S1. PF5 I/O Port F5: I/O port. 1 I2
ページ14に含まれる内容の要旨
TMP92CZ26A Table 2.2.1 Pin names and functions (4/6) Number of Pin name I/O Functions Pins PK0 Output Port K0: Output port. 1 LCP0 Output Signal for LCD driver. PK1 Output Port K1: Output port. 1 LLOAD Output Signal for LCD driver.: Data load signal PK2 Output Port K2: Output port. 1 LFR Output Signal for LCD driver. PK3 Output Port K3: Output port. 1 LVSYNC Output Signal for LCD driver. : Vertical sync signal PK4 Output Port K4: Output port. 1 LHSYNC Input Signal for LCD
ページ15に含まれる内容の要旨
TMP92CZ26A Table 2.2.1 Pin names and functions (5/6) Number of Pin name I/O Functions Pins PR3 I/O Port R3: I/O port. 1 SPCLK Output Clock output pin of SD card. PT0 to PT7 I/O Port T0 to T7: I/O port. 8 LD8 to LD15 Output Data bus for LCD driver: LD8 to LD15. PU0 to PU4,PU6 I/O Port U0 to U4 , U6: I/O port 6 LD16 to LD20,LD22 Output Data bus for LCD driver: LD16 to LD20, LD22. PU5 I/O Port U5: I/O port 1 LD21 Output Data bus for LCD driver: LD21 PU7 I/O Port U7: I/O port L
ページ16に含まれる内容の要旨
TMP92CZ26A Table 2.2.1 Pin names and functions (6/6) Number of Pin name I/O Functions Pins Data pin connected to USB. D+, D- 2 I/O In case USB is not used, connect both pins to pull-up(DVCC3A) or pull-down resistor for protect current flows it. CLKOUT 1 Output Internal clock output pin. Operation mode; Fix to AM1=”0”,AM0=”1” for 16 bit external bus starting. AM1,AM0 2 Input Fix to AM1=”1”,AM0=”0” is prohibit to set. Fix to AM1=”1”,AM0=”1” for BOOT (32 bit internal Mask ROM) star
ページ17に含まれる内容の要旨
TMP92CZ26A 3. Operation This section describes the basic components, functions and operation of the TMP92CZ26A. 3.1 CPU The TMP92CZ26A contains an advanced high-speed 32-bit CPU (900/H1 CPU) 3.1.1 CPU Outline 900/H1 CPU is high-speed and high-performance CPU based on 900/L1 CPU. 900/H1 CPU has expanded 32-bit internal data bus to process Instructions more quickly. Outline is as follows: Table 3.1.1Outline of TMP92CZ26A Parameter TMP92CZ26A Width of CPU Address Bus 24-bit W
ページ18に含まれる内容の要旨
TMP92CZ26A 3.1.2 Reset Operation When resetting the TMP92CZ26A microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input Low for at least 20 system clocks (32µs at X1=10MHz). At reset, since the clock doublers (PLL0) is bypassed and clock-gear is set to 1/16, system clock operates at 625 kHz(X1=10MHz). When the Reset has been accepted, the CPU performs the fol
ページ19に含まれる内容の要旨
TMP92CZ26A Figure 3.1.1 TMP92CZ26A Reset timing chart 92CZ26A-16 f sys Sampling RESET Sampling f (15.5∼16.5) Clock SYS A23∼0 0FFFF00H CS0,1, 3 CS2 DATA-IN DATA-IN D0∼15 RD SRxxB (After reset is released, it is started from 1 wait read cycle) D0∼15 DATA-OUT WRxx SRWR SRxxB : High-Z
ページ20に含まれる内容の要旨
TMP92CZ26A This LSI has the restriction for the order of supplying power. Be sure to supply external 3.3V power with 1.5V power is supplied. Power On Stand-by Mode (PMC) Power Off DVCC1A 1.5V DVCC1B Power DVCC1C Power supply is rising with Power supply is falling with in 100mS, and stabilizes. in 100mS, and stabilizes. After 1.5V power After 1.5V power supply is rising, supply is falling, set set 3.3V to ON. 3.3V to OFF. 3.3V DVCC3A Power DV
