ページ1に含まれる内容の要旨
Features
• Programmable Audio Output for Interfacing with Common Audio DAC
– PCM Format Compatible
2
–I S Format Compatible
� 8-bit MCU C51 Core-based (F = 20 MHz)
MAX
� 2304 Bytes of Internal RAM
� 64K Bytes of Code Memory
– AT89C5132: Flash (100K Write/Erase Cycles)
� 4K Bytes of Boot Flash Memory (AT89C5132)
– ISP: Download from USB (standard) or UART (option)
� USB Rev 1.1 Device Controller
USB
– “Full Speed” Data Transmission
� Built-in PLL
Microcontroller
®
� MultiMedia Card Interface C
ページ2に含まれる内容の要旨
3. Block Diagram Figure 3-1. AT89C5132 Block Diagram INT0 INT1 V V UV UVSS AV AVSS AREF AIN1:0 TXD RXD T0 T1 SS MISO MOSI SCK SCL SDA DD SS DD DD 11 1112 1 222 11 Interrupt Flash Handler Unit UART RAM 10-bit A-to-D Timers 0/1 SPI/DataFlash TWI 64K Bytes and 2304 Bytes Converter Watchdog Controller Controller BRG Flash Boot 4K Bytes C51 (X2 CORE) 8-BIT INTERNAL BUS I/O 2 I S/PCM USB MMC Keyboard Ports Audio Interface Controller Interface Interface IDE Clock and PLL Interface Unit 3 FILT X1 X2 RS
ページ3に含まれる内容の要旨
AT89C5132 4. Pin Description Figure 4-1. AT89C5132 80-pin TQFP Package ALE 1 60 P4.5 ISP 2 59 P4.4 P1.0/KIN0 3 58 P2.2/A10 P1.1/KIN1 4 57 P2.3/A11 P1.2/KIN2 5 56 P2.4/A12 P1.3/KIN3 6 55 P2.5/A13 P1.4 7 54 P2.6/A14 P1.5 8 53 P2.7/A15 P1.6/SCL 9 52 VSS P1.7/SDA 10 51 VDD TQFP80 VDD 11 50 MCLK PVDD 12 49 MDAT FILT 13 48 MCMD PVSS 14 47 RST VSS 15 SCLK 46 X2 16 45 DSEL X1 17 44 DCLK TST DOUT 18 43 UVDD 19 42 VSS UVSS 20 41 VDD 3 4173ES–USB–09/07 D+ 21 80 P5.1 D- 22 79 P5.0 VDD 23 78 P0.0/AD0 VSS 2
ページ4に含まれる内容の要旨
(1) Figure 4-2. AT89C5132 84-pin PLCC ALE 12 74 NC ISP 13 73 P4.5 P1.0/KIN0 14 72 P4.4 P1.1/KIN1 15 71 P2.2/A10 P1.2/KIN2 16 70 P2.3/A11 P1.3/KIN3 17 69 P2.4/A12 P1.4 18 68 P2.5/A13 P1.5 19 67 P2.6/A14 P1.6/SCL 20 66 P2.7/A15 P1.7/SDA 21 65 VSS PLCC84 VDD 22 64 VDD PAVDD 23 63 MCLK FILT 24 62 MDAT PAVSS 25 61 MCMD VSS 26 60 RST X2 27 59 SCLK NC 28 58 DSEL X1 29 57 DCLK TST 30 56 DOUT UVDD 31 55 VSS UVSS 32 54 VDD Note: 1. For development board only. 4.1 Signals All the AT89C5132 signals are det
ページ5に含まれる内容の要旨
AT89C5132 Signal Alternate Name Type Description Function Port 2 P2.7:0 I/O A15:8 P2 is an 8-bit bidirectional I/O port with internal pull-ups. RXD TXD INT0 Port 3 INT1 P3.7:0 I/O P3 is an 8-bit bidirectional I/O port with internal pull-ups. T0 T1 WR RD MISO Port 4 MOSI P4.7:0 I/O P4 is an 8-bit bidirectional I/O port with internal pull-ups. SCK SS Port 5 P5.3:0 I/O - P5 is a 4-bit bidirectional I/O port with internal pull-ups. Table 2. Clock Signal Description Signal Alternate Name Type
ページ6に含まれる内容の要旨
Signal Alternate Name Type Description Function Timer 0 External Clock Input T0 I When timer 0 operates as a counter, a falling edge on the T0 pin increments P3.4 the count. Timer 1 External Clock Input T1 I When timer 1 operates as a counter, a falling edge on the T1 pin increments P3.5 the count. Table 4. Audio Interface Signal Description Signal Alternate Name Type Description Function DCLK O DAC Data Bit Clock - DOUT O DAC Audio Data - DAC Channel Select Signal DSEL O - DSEL is the sam
ページ7に含まれる内容の要旨
AT89C5132 Table 7. UART Signal Description Signal Alternate Name Type Description Function Receive Serial Data RXD I/O RXD sends and receives data in serial I/O mode 0 and receives data in serial P3.0 I/O modes 1, 2 and 3. Transmit Serial Data TXD O TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O P3.1 modes 1, 2 and 3. Table 8. SPI Controller Signal Description Signal Alternate Name Type Description Function SPI Master Input Slave Output Data Line MISO I
ページ8に含まれる内容の要旨
Table 11. Keypad Interface Signal Description Signal Alternate Name Type Description Function Keypad Input Lines KIN3:0 I Holding one of these pins high or low for 24 oscillator periods triggers a P1.3:0 keypad interrupt. Table 12. External Access Signal Description Signal Alternate Name Type Description Function Address Lines A15:8 I/O Upper address lines for the external bus. P2.7:0 Multiplexed higher address and data lines for the IDE interface. Address/Data Lines AD7:0 I/O Multiplexed
ページ9に含まれる内容の要旨
AT89C5132 Table 14. Power Signal Description Signal Alternate Name Type Description Function Digital Supply Voltage VDD PWR - Connect these pins to +3V supply voltage. Circuit Ground VSS GND - Connect these pins to ground. Analog Supply Voltage AVDD PWR - Connect this pin to +3V supply voltage. Analog Ground AVSS GND - Connect this pin to ground. PLL Supply voltage PVDD PWR - Connect this pin to +3V supply voltage. PLL Circuit Ground PVSS GND - Connect this pin to ground. USB Supply Vol
ページ10に含まれる内容の要旨
4.2 Internal Pin Structure Table 15. Detailed Internal Pin Structure (1) Circuit Type Pins VDD Input TST VDD P Watchdog Output Input/Output RST VSS VDD VDD VDD 2 osc periods (2) P1 Latch Output P P P (3) 1 2 3 P2 Input/Output P3 P4 N P53:0 VSS VDD P0 P MCMD MDAT Input/Output ISP N PSEN VSS VDD ALE SCLK P DCLK Output DOUT DSEL N MCLK VSS D+ Input/Output D+ D- D- Notes: 1. For information on resistors value, input/output levels, and drive capability, refer to the Section “DC Characteristics”, p
ページ11に含まれる内容の要旨
AT89C5132 5. Address Spaces The AT8xC5132 derivatives implement four different address spaces: � Program/Code Memory � Boot Memory � Data Memory � Special Function Registers (SFRs) 5.0.1 Code Memory The AT89C5132 implements 64K Bytes of on-chip program/code memory in Flash technology. The Flash memory increases ROM functionality by enabling in-circuit electrical erasure and pro- gramming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is ge
ページ12に含まれる内容の要旨
Peripherals The AT8xC5132 peripherals are briefly described in the following sections. For further details on how to interface (hardware and software) to these peripherals, please refer to the AT8xC5132 complete datasheet. Clock Generator System The AT8xC5132 internal clocks are extracted from an on-chip PLL fed by an on-chip oscillator. Four clocks are generated respectively for the C51 core, the audio interface, and the other peripherals. The C51 and peripheral clocks are derived from the
ページ13に含まれる内容の要旨
AT89C5132 Serial I/O Interface The AT89C5132 implements a serial port with its own baud rate generator providing one single synchronous communication mode and three full-duplex Universal Asynchronous Receiver Transmitter (UART) communication modes. It is provided for the following purposes: � In System Programming. � Remote control of the AT89C5132 by a host. Serial Peripheral The AT89C5132 implements a Serial Peripheral Interface (SPI) supporting master and slave modes. It is provided for
ページ14に含まれる内容の要旨
6. Electrical Characteristics 6.1 Absolute Maximum Ratings *NOTICE: Stressing the device beyond the “Absolute Maxi- Storage Temperature ..................................... -65°C to +150°C mum Ratings” may cause permanent damage. Voltage on any other Pin to V -0.3 to +4.0V These are stress ratings only. Operation beyond SS ..................................... the “operating conditions” is not recommended I per I/O Pin ................................................................. 5 mA
ページ15に含まれる内容の要旨
AT89C5132 Table 1. Digital DC Characteristics V = 2.7 to 3.3V , T = -40 to +85°C DD A (1) Symbol Parameter Min Typ Max Units Test Conditions Input Leakage Current (P0, ALE, MCMD, I MDAT, MCLK, SCLK, DCLK, DSEL, 10 μA 0.45< V < V LI IN DD DOUT) Logical 1 to 0 Transition Current I -650 μA Vin = 2.0 V TL (P1, P2, P3, P4 and P5) R Pull-Down Resistor 50 90 200 kΩ RST C Pin Capacitance 10 pF T = 25°C IO A V V Data Retention Limit 1.8 V RET DD V < 3.3 V X1 / X2 mode DD 6.5 / 10.5 12 MHz (3) I Op
ページ16に含まれる内容の要旨
Figure 6-2. I Test Condition, Idle Mode DL VDD VDD I DL RST PVDD UVDD VSS AVDD (NC) X2 VDD Clock Signal X1 P0 VSS PVSS TST UVSS AVSS VSS All other pins are unconnected Figure 6-3. I Test Condition, Power-Down Mode PD VDD VDD I PD RST PVDD UVDD VSS AVDD VDD (NC) X2 X1 P0 MCMD VSS PVSS MDAT UVSS AVSS TST VSS All other pins are unconnected 6.2.3 A-to-D Converter Table 2. A-to-D Converter DC Characteristics V = 2.7 to 3.3V , T = -40 to +85°C DD A Symbol Parameter Min Typ Max Units Test Conditions
ページ17に含まれる内容の要旨
AT89C5132 6.2.4 Oscillator and Crystal 6.2.4.1 Schematic Figure 6-4. Crystal Connection X1 C1 Q C2 VSS X2 Note: For operation with most standard crystals, no external components are needed on X1 and X2. It may be necessary to add external capacitors on X1 and X2 to ground in special cases (max 10 pF). X1 and X2 may not be used to drive other circuits. 6.2.4.2 Parameters Table 3. Oscillator and Crystal Characteristics V = 2.7 to 3.3V , T = -40 to +85°C DD A Symbol Parameter Min Typ Max Unit
ページ18に含まれる内容の要旨
6.2.5.2 Parameters Table 4. PLL Filter Characteristics V = 2.7 to 3.3V , T = -40 to +85°C DD A Symbol Parameter Min Typ Max Unit R Filter Resistor 100 Ω C1 Filter Capacitance 1 10 nF C2 Filter Capacitance 2 2.2 nF 6.2.6 USB Connection 6.2.6.1 Schematic Figure 6-6. USB Connection VDD To Power R VBUS FS Supply D+ D+ R USB D- D- R USB GND VSS 6.2.6.2 Parameters Table 16. USB Characteristics V = 3 to 3.3 V, T = -40 to +85°C DD A Symbol Parameter Min Typ Max Unit R USB Termination Resistor 27 Ω US
ページ19に含まれる内容の要旨
AT89C5132 6.3 AC Characteristics 6.3.1 External 8-bit Bus Cycles 6.3.1.1 Definition of Symbols Table 6. External 8-bit Bus Cycles Timing Symbol Definitions Signals Conditions A Address H High D Data In L Low L ALE V Valid Q Data Out X No Longer Valid RRD ZFloating WWR 6.3.1.2 Timings Test conditions: capacitive load on all pins = 50 pF. Table 7. External 8-bit Bus Cycle – Data Read AC Timings V = 2.7 to 3.3V, T = -40° to +85°C DD A Variable Clock Variable Clock Standard Mode X2 Mode Symbol P
ページ20に含まれる内容の要旨
Table 8. External 8-bit Bus Cycle – Data Write AC Timings V = 2.7 to 3.3V, T = -40° to +85°C DD A Variable Clock Variable Clock Standard Mode X2 Mode Symbol Parameter Min Max Min Max Unit T Clock Period 50 50 ns CLCL T ALE Pulse Width 2·T -15 T -15 ns LHLL CLCL CLCL T Address Valid to ALE Low T -20 0.5·T -20 ns AVLL CLCL CLCL T Address hold after ALE Low T -20 0.5·T -20 ns LLAX CLCL CLCL T ALE Low to WR Low 3·T -30 1.5·T -30 ns LLWL CLCL CLCL T WR Pulse Width 6·T -25 3·T -25 ns WLWH CLCL CLCL
