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Intel Itanium 2 Processor
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Intel Itanium 2 Processor 1.66 GHz with 9 MB L3 Cache
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Intel Itanium 2 Processor 1.66 GHz with 6 MB L3 Cache
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Intel Itanium 2 Processor 1.6 GHz with 9 MB L3 Cache
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Intel Itanium 2 Processor 1.6 GHz with 6 MB L3 Cache
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Intel Itanium 2 Processor 1.5 GHz with 6 MB L3 Cache
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Intel Itanium 2 Processor 1.5 GHz with 4 MB L3 Cache
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Intel Itanium 2 Processor 1.4 GHz with 4 MB L3 Cache
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Intel Itanium 2 Processor 1.3 GHz with 3 MB L3 Cache
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Intel I
ページ2に含まれる内容の要旨
® INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
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Contents 1 Introduction.......................................................................................................................11 1.1 Overview .............................................................................................................11 1.2 Processor Abstraction Layer ...............................................................................11 1.3 Mixing Processors of Different Frequencies and Cache Sizes ...........................12 1.4 Terminology........
ページ4に含まれる内容の要旨
6.1.3 SMBus Device Addressing.....................................................................81 6.2 Processor Information ROM................................................................................82 6.3 Scratch EEPROM ...............................................................................................85 6.4 Processor Information ROM and Scratch EEPROM Supported SMBus Transactions ...........................................................................................
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A.1.37 ID[9:0]# (I) ..............................................................................................99 A.1.38 IDS# (I) ...................................................................................................99 A.1.39 IGNNE# (I)............................................................................................100 A.1.40 INIT# (I) ................................................................................................100 A.1.41 INT (I) ....................
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® 5-2 Itanium 2 Processor Package Thermocouple Location.....................................77 6-1 Logical Schematic of SMBus Circuitry ................................................................80 Tables ® 2-1 Itanium 2 Processor System Bus Signal Groups ..............................................16 ® 2-2 Itanium 2 Processor Package Specifications....................................................17 ® 2-3 Itanium 2 Processor Power Supply Specifications..................................
ページ7に含まれる内容の要旨
® 6-2 Thermal Sensing Device SMBus Addressing on the Itanium 2 Processor .......81 ® 6-3 EEPROM SMBus Addressing on the Itanium 2 Processor ...............................82 6-4 Processor Information ROM Format ...................................................................82 6-5 Current Address Read SMBus Packet................................................................86 6-6 Random Address Read SMBus Packet ..............................................................86 6-7 Byte Writ
ページ8に含まれる内容の要旨
Revision History Revision No. Description Date -001 Initial release of this document. July 2002 -002 Updated content to include information pertaining to Itanium 2 processor June 2003 (1.5 GHz, 6 MB), Itanium 2 processor (1.4 GHz, 4 MB) and Itanium 2 processor (1.3 GHz, 3 MB). ® -003 Updated content to include information pertaining to Itanium 2 November 2004 processor (1.5 GHz, 4 MB) and Itanium 2 processor (1.6 GHz, 6 MB and 9MB). ® -004 Updated content to include information pertai
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® ® Intel Itanium 2 Processor ® ® Intel Itanium 2 Processor 1.66 GHz with 9 MB L3 Cache ® ® Intel Itanium 2 Processor 1.66 GHz with 6 MB L3 Cache ® ® Intel Itanium 2 Processor 1.6 GHz with 9 MB L3 Cache ® ® Intel Itanium 2 Processor 1.6 GHz with 6 MB L3 Cache ® ® Intel Itanium 2 Processor 1.5 GHz with 6 MB L3 Cache ® ® Intel Itanium 2 Processor 1.5 GHz with 4 MB L3 Cache ® ® Intel Itanium 2 Processor 1.4 GHz with 4 MB L3 Cache ® ® Intel Itanium 2 Processor 1.3 GHz with 3 MB L3 Cache ® ® Intel I
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10 Datasheet
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1 Introduction 1.1 Overview The Itanium 2 processor employs Explicitly Parallel Instruction Computing (EPIC) design concepts for a tighter coupling between hardware and software. In this design style, the interface between hardware and software is designed to enable the software to exploit all available compile- time information, and efficiently deliver this information to the hardware. It addresses several fundamental performance bottlenecks in modern computers, such as memory latency, memor
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Introduction 1.3 Mixing Processors of Different Frequencies and Cache Sizes All Itanium 2 processors on the same system bus are required to have the same cache size (9 MB, 6 MB, 4 MB, 3 MB or 1.5 MB) and identical core frequency. Mixing components of different core frequencies and cache sizes is not supported and has not been validated by Intel. Operating system support for multiprocessing with mixed components should also be considered. While Intel has done nothing to specifically prevent p
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Introduction 1.6 Reference Documents The reader of this specification should also be familiar with material and concepts presented in the following documents: Title Document Number ® ® Intel Itanium 2 Processor Specification Update 251141 ® ® Intel Itanium Architecture Software Developer’s Manual, Volume 1: 245317 Application Architecture ® ® Intel Itanium Architecture Software Developer’s Manual, Volume 2: System 245318 Architecture ® ® Intel Itanium Architecture Software Developer’s Manua
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Introduction 14 Datasheet
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2 Electrical Specifications This chapter describes the electrical specifications of the Itanium 2 processor. ® 2.1 Itanium 2 Processor System Bus Most Itanium 2 processor signals use the Itanium processor’s assisted gunning transceiver logic (AGTL+) signaling technology. The termination voltage, V , is generated on the baseboard CTERM and is the system bus high reference voltage. The buffers that drive most of the system bus signals on the Itanium 2 processor are actively driven to V during a
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Electrical Specifications .. ® Table 2-1. Itanium 2 Processor System Bus Signal Groups Group Name Signals 1 AGTL+ Input Signals BPRI#, BR[3:1]#, DEFER#, GSEQ#, ID[9:0]#, IDS#, RESET# , RS[2:0]#, RSP#, TRDY# 1 AGTL+ I/O Signals A[49:3]#, ADS#, AP[1:0]#, BERR#, BINIT#, BNR#, BPM[5:0]# , BR0#, D[127:0]#, DBSY#, DEP[15:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[5:0]#, RP#, SBSY#, STBN[7:0]#, STBP[7:0]#, TND# AGTL+ Output Signals FERR#, THRMTRIP#, DBSY[1:0]#, DRDY[1:0]#, SBSY[1:0]# Special AGTL+ Asynchro
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Electrical Specifications V System bus termination voltage. CTERM GND System ground. N/C No connection can be made to these pins. TERMA, TERMB The Itanium 2 processor uses two pins to control the on-die termination function, TERMA and TERMB. Both of these termination pins must be pulled to VCTERM in order to terminate the system bus using the on-die termination resistors. Both of these termination pins must be pulled to GND in order to use off-die termination. TUNER1, TUNER2 TUNER1 is used t
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Electrical Specifications NOTES: 1. This is the tolerance requirement, across a 200 MHz bandwidth, at the processor pins. The requirement at the processor pins accounts for voltage drops (and impedance discontinuities) at the processor pins and to the processor core. In addition to the ±1.5% DC tolerance, there is a ±3.5% AC tolerance for a total of ±5% tolerance. ® 2. The Itanium 2 processor system bus is terminated at each end of the system bus. The Itanium 2 processor supports both on- die
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Electrical Specifications Table 2-4. AGTL+ Signals DC Specifications (Sheet 2 of 2) Core Symbol Parameter Minimum Typ Maximum Unit Notes Frequency 5 I Leakage Current All ±100 µA L 6 C AGTL+ Pad Capacitance 900 MHz 3 pF AGTL+ 6 1.0 GHz 3 pF 6 1.3 GHz 1.5 pF 6 1.4 GHz 1.5 pF 6 1.5 GHz 1.5 pF 6 1.6 GHz 1.5 pF 6 1.66 GHz 1.5 pF NOTES: 1. The typical transition point between V and V assuming 125 mV V uncertainty for ODT. V and V levels are IL IH REF REF_high REF_low V ±100 mV respectively, for a s
ページ20に含まれる内容の要旨
Electrical Specifications Table 2-8. SMBus DC Specifications Symbol Parameter Minimum Typ Maximum Unit Notes 3.3V V for the System Management 3.14 3.3 3.47 V 3.3V ±5% CC Components V Input Low Voltage –0.3 0.3*3.3V V IL V Input High Voltage 2.31 3.47 V Max = IH 3.3 +5% Min + 0.7*3.3V V Output Low Voltage 0.4 V OL I 3.3V Supply Current 5.0 30.0 mA 3.3V 1 I Output Low Current 3 mA OL 2 I Output Low Current 6 mA OL2 I Input Leakage Current 10 µA LI I Output Leakage Current 10 µA LO NOTES: 1. The v
