Sony CDX-605 user manual

User manual for the device Sony CDX-605

Device: Sony CDX-605
Category: Car Video System
Manufacturer: Sony
Size: 0.85 MB
Added : 7/3/2013
Number of pages: 8
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Summaries

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Abstracts of contents
Summary of the content on the page No. 1

CDX-605
SERVICE MANUAL US Model
Model Name Using Similar Mechanism CDX-505RF
CD Drive Mechanism Type MG-250C-137
Optical Pick-up Name KSS-521A/J2N
SPECIFICATIONS
System Compact disc digital audio system
Frequency response 10 – 20,000 Hz
Wow and flutter Below the measurable limit
Signal-to-noise ratio 94 dB
Outputs BUS control output (8 pins)
Analog audio output (RCA pin)
Current drain 800 mA (during CD playback)
800 mA (during loading or ejecting a disc)
Operating temperature – 10 °C to + 55 °C

Summary of the content on the page No. 2

CDX-605 7-3. SCHEMATIC DIAGRAM – RF Section – • See page 17 for Waveforms. • See page 31 for IC Block Diagrams. (Page 27) – 21 – – 22 –

Summary of the content on the page No. 3

CDX-605 7-6. SCHEMATIC DIAGRAM – MAIN Section (1/2) – • See page 17 for Waveforms. • See page 31 for IC Block Diagrams. (Page 22) – 27 – – 28 –

Summary of the content on the page No. 4

CDX-605 7-7. SCHEMATIC DIAGRAM – MAIN Section (2/2) – • See page 17 for Waveforms. • See page 31 for IC Block Diagrams. – 29 – – 30 –

Summary of the content on the page No. 5

CDX-605 • IC Block Diagrams IC52 BA6287F (RF BOARD) IC301 BA6287F (MAIN BOARD) IC11 CXA1992BR (RF BOARD) OUT1 1 8 GND 39 38 37 36 35 34 33 32 31 30 29 28 27 VEE – + VM 2 7 OUT2 RF SUMMING PD2 IV PD1 IV AMP AMP AMP DRIVER DRIVER FE_BIAS SENS2 40 26 TSD VCC APC VCC 3 6 VREF CONTROL LOGIC IIL VEE F – SENS1 41 ↓ 25 LASER POWER CONTROL + TTL F IV AMP VCC POWER SAVE VCC VCC FE AMP E – 42 24 C. OUT FIN 4 5 RIN + E IV AMP VEE + – DFCT EI 43 23 XRST + VEE – LEVEL S VEE VEE VEE 44 22 DATA VEE FO. BIAS WI

Summary of the content on the page No. 6

IC102 SM5852FS-E2 (MAIN BOARD) IC204 BA8272F-E2 (MAIN BOARD) 16 DB/DS LRCI 1 INPUT BCKI 2 15 MOD2 INTERFACE DIGITAL 14 13 12 11 10 9 8 3 14 MOD1 DI SIGNAL 13 OPT PROCESSOR SYSTEM 4 CLOCK CLK VDD 12 RESET 5 VSS SWITCH 11 LRCO SEQUENTIAL RSTN 6 OUTPUT 10 BCKO CONTROL INTERFACE TESTN 7 9 DOUT 1 2 3 4 5 6 7 MUTE MUTEN 8 CONTROL MODE CONTROL IC401 TC9464FN-EL (MAIN BOARD) 20 19 18 17 16 15 14 13 24 23 22 21 MICROCOMPUTER INTERFACE OSC INTERFACE CIRCUIT CIRCUIT DIGITAL FILTER CIRCUIT TIMING ATTENUATOR

Summary of the content on the page No. 7

7-8. IC PIN FUNCTION DESCRIPTION • MAIN BOARD IC302 CXP84124-078Q (SYSTEM CONTROLLER) Pin No. Pin Name I/O Function Sled limit in detect switch (SW1) input terminal 1 LIM.SW I “L”: When the optical pick-up is inner position 2 BUSON I Bus on/off control signal input from the SONY bus interface (IC204) “H”: bus on 3 EJECT I Eject switch (SW303) input terminal “H” active Save end detect switch (SW12) input terminal 4 LOAD1 I “L”: When completion of the disc chucking operation Chucking en

Summary of the content on the page No. 8

Pin No. Pin Name I/O Function 50 SO O Serial data output to the SONY bus interface (IC204) 51 SQCLK O Subcode Q data reading clock signal output to the CXD2530Q (IC101) 52 SUBQ I Subcode Q data input from the CXD2530Q (IC101) 53 — O Not used (open) 54 — I Not used (fixed at “H”) Magazine eject operation completion detect switch (SW301) input terminal 55 MGLK I “L”: eject completed 56 SCOR I Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101) 57 SENS2 I Internal status signal (s


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