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NI 5412 Specifications
NI PXI/PCI-5412 14-Bit 100 MS/s Arbitrary Waveform Generator
Unless otherwise noted, the following conditions were used for each
specification:
• Interpolation set to maximum allowed factor for a given sample rate.
Signals terminated with 50 Ω .
Low-Gain Amplifier Path set to 2 V , and High-Gain Amplifier
pk-pk
Path set to 12 V .
pk-pk
Sample clock set to 100 MS/s.
Typical values are representative of an average unit operating at room
temperature. Specifications a
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CH 0 (Channel 0 Analog Output, Front Panel Connector) Table 1. Specification Value Comments Number of 1 — Channels Connector SMB (jack) — Output Voltage Characteristics Output Paths The software-selectable Main Output Path setting provides — full-scale voltages from 12.00 V to 5.64 mV into a pk-pk pk-pk 50 Ω load. NI-FGEN uses either the Low-Gain Amplifier or the High-Gain Amplifier when the Main Output Path is selected, depending on the Gain attribute. DAC 14 bits — Resolution Amplitude an
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Table 1. (Continued) Specification Value Comments Maximum Output Voltage Maximum Path Load Maximum Output Voltage (V ) The Maximum pk-pk Output Output Voltage Low- 50 Ω ±1.000 Voltage of the NI 5412 is Gain determined by 1 kΩ ±1.905 Amplifier the Amplitude Range and the Open ±2.000 Offset Range. High- 50 Ω ±6.000 Gain 1 kΩ ±11.43 Amplifier Open ±12.00 Accuracy DC Accuracy ±0.2% of Amplitude ± 0.05% of Offset ± 500 µV Calibrated for (within ±10 °C of self-calibration temperature) high
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Table 1. (Continued) Specification Value Comments Frequency and Transient Response Bandwidth 20 MHz –3 dB Digital Software-selectable Finite Impulse Response (FIR) filter. — Interpolation Available interpolation factors are 2, 4, or 8. Filter Passband Low-Gain and High-Gain Amplifiers Path — Flatness ±1.0 dB from DC to 6 MHz Pulse Path All values are Response typical. Low-Gain Amplifier High-Gain Amplifier Measured with a 1 m RG-223 Rise/Fall Time <20 ns <20 ns cable. Aberration <5% <5% N
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2.0 1.6 1.2 0.8 0.4 0.0 –0.4 –0.8 –1.2 –1.6 –2.0 0 0.2 0.4 0.6 0.8 1.0 Time (µs) Figure 1. Pulse Response, Low-Gain Amplifier Path 50 Ω Load © National Instruments Corporation 5 NI 5412 Specifications Amplitude (V)
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Table 1. (Continued) Specification Value Comments Suggested Maximum Frequencies for Common Functions Function Path — Low-Gain Amplifier High-Gain Amplifier Sine 20 MHz 20 MHz Square 5 MHz 5 MHz Ramp 1 MHz 1 MHz Triangle 1 MHz 1 MHz Spectral Characteristics Spurious-Free Path Amplitude Dynamic –1 dBFS. Range Measured from (SFDR) DC to 50 MHz. without SFDR without Harmonics Low-Gain Amplifier High-Gain Amplifier harmonics at low amplitudes is 1 MHz –70 dBc –70 dBc limited by a –148 dBm/
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Table 1. (Continued) Specification Value Comments Spectral Characteristics (Continued) Average Noise Amplitude Average Noise Density Range Average Noise Density Density at small amplitudes is nV dBFS/ --- ---- --- - limited by a Path V dBm Hz dBm/Hz Hz pk-pk –148 dBm/Hz noise floor. Low-Gain 2 10 45 –134 –144 High- 12 25.6 251 –119 –145 Gain Sample Clock Table 2. Specification Value Comments Sources 1. Internal, Divide-by-N (N ≥ 1) Refer to the Onboard Clock 2. Internal, DDS-based, Hig
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Table 2. (Continued) Specification Value Comments Sample Rate Range and Resolution Sample Clock — Source Sample Rate Range Sample Rate Resolution Divide-by-N 23.84 S/s to 100 MS/s Settable to (100 MS/s) / N (1 ≤ N ≤ 4,194,304) High- 10 S/s to 100 MS/s 1.06 µHz Resolution CLK IN 200 kS/s to 105 MS/s Resolution determined by external clock source. NI PXI-5412 10 S/s to 105 MS/s External Sample Clock duty PXI Star cycle tolerance 40% to 60%. Trigger NI PXI-5412 10 S/s to 20 MS/s PXI_Trig<0..7>
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Table 2. (Continued) Specification Value Comments System Phase Noise and Jitter (10 MHz Carrier) Sample Clock System Phase Noise 1. High- Source Density Resolution System Output Jitter (dBc/Hz) Offset specifications (Integrated from vary with 100 Hz 1 kHz 10 kHz 100 Hz to 100 kHz) Sample Rate. NI PXI-5412 –100 –118 –120 <6 ps rms 2. All values are typical. NI PCI-5412 –90 –110 –120 <7 ps rms External Cycle-Cycle Jitter ±300 ps — Sample Clock Period Jitter ±1 ns Input Jitter Tolerance Sa
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Onboard Clock (Internal VCXO) Table 3. Specification Value Comments Clock Source Internal sample clocks can either be locked to a Reference — Clock using a phase-locked loop or be derived from the onboard VCXO frequency reference. Frequency ±25 ppm — Accuracy Phase-Locked Loop (PLL) Reference Clock Table 4. Specification Value Comments Sources 1. NI PXI-5412—PXI_CLK10 (backplane connector) The PLL NI PCI-5412—RTSI_7 (RTSI_CLK) Reference Clock provides the 2. CLK IN (SMB front panel conne
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CLK IN (Sample Clock and Reference Clock Input, Front Panel Connector) Table 5. Specification Value Comments Connector SMB (jack) — Direction Input — Destinations 1. Sample Clock — 2. PLL Reference Clock Frequency 1 MHz to 105 MHz (Sample Clock destination and — Range sine waves) 200 kHz to 105 MHz (Sample Clock destination and square waves) 5 MHz to 20 MHz (PLL Reference Clock destination) Input Voltage Sine wave: 0.65 V to 2.8 V into 50 Ω — pk-pk pk-pk Range (0 dBm to +13 dBm) Square wave:
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PFI 0 and PFI 1 (Programmable Function Interface, Front Panel Connectors) Table 6. Specification Value Comments Connectors Two SMB (jack) — Direction Bi-directional — Frequency DC to 105 MHz — Range As an Input (Trigger) Destinations Start Trigger — Maximum –2 V to +7 V — Input Overload V 2.0 V IH V 0.8 V IL Input 1 kΩ Impedance As an Output (Event) Sources 1. Sample Clock divided by integer K (1 ≤ K ≤ 4,194,304) — 2. Sample Clock Timebase (100 MHz) divided by integer M (2 ≤ M ≤ 4,194,304) 3.
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Table 6. (Continued) Specification Value Comments V Minimum: 2.9 V (open load), 1.4 V (50 Ω load) Output drivers are OH +3.3 V TTL compatible. Measured with a V Maximum: 0.2 V (open load), 0.2 V (50 Ω load) 1 m cable. OL Rise/Fall Time ≤2.0 ns Load of 10 pF. (20% to 80%) Start Trigger Table 7. Specification Value Comments Sources 1. PFI<0..1> (SMB front panel connectors) — 2. NI PXI-5412—PXI_Trig<0..7> (backplane connector) NI PCI-5412—RTSI<0..7> 3. NI PXI-5412—PXI Star trigger (backplan
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Table 7. (Continued) Specification Value Comments Delay from Interpolation Factor Typical Delay Refer to t at s2 Start Trigger to NI Signal Digital Interpolation Filter 43 Sample Clock CH 0 Analog Generators disabled. Periods + 110 ns Output Help»Devices» NI 5412» 2 57 Sample Clock NI -5412» Periods + 110 ns Triggering» 4 63 Sample Clock Trigger Timing. Periods + 110 ns 8 64 Sample Clock Periods + 110 ns Trigger Exporting Exported A signal used as a trigger can be routed out to any
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Markers Table 8. Specification Value Comments Destinations 1. PFI<0..1> (SMB front panel connectors) — 2. NI PXI-5412—PXI_Trig<0..6> (backplane connector) NI PCI-5412—RTSI<0..6> Quantity One Marker per Segment. — Quantum Marker position must be placed at an integer multiple of — four samples. Width >150 ns. Refer to t at NI Signal Generators Help» — m2 Devices»NI 5412»NI -5412»Waveform Generation»Marker Events. Skew With Respect to Analog Refer to t at m1 Destination Output NI Signal
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Waveform and Instruction Memory Utilization Table 9. Specification Value Comments Memory Usage The NI 5412 uses the Synchronization and Memory Core — (SMC) technology in which waveforms and instructions share onboard memory. Parameters, such as number of segments in sequence list, maximum number of waveforms in memory, and number of samples available for waveform storage, are flexible and user defined. Onboard 8 MB standard: 32 MB option: 256 MB option: — Memory Size 8,388,608 bytes 33,554
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Table 9. (Continued) Specification Value Comments Loop Count 1 to 16,777,215. — Burst trigger: Unlimited Quantum Waveform size must be an integer multiple of four samples. — Memory Limits 8 MB Standard 32 MB Option 256 MB Option All trigger modes except where Arbitrary 4,194,176 16,777,088 134,217,600 noted. Waveform Samples Samples Samples Mode, Maximum Waveform Memory Arbitrary 4,194,120 16,777,008 134,217,520 Condition: One Sequence Samples Samples Samples or two segments Mode, in a
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Calibration Table 10. Specification Value Comments Self-Calibration An onboard, 24-bit ADC and precision voltage reference are — used to calibrate the DC gain and offset. The self-calibration is initiated by the user through the software and takes approximately 75 seconds to complete. External The External Calibration calibrates the VCXO, voltage — Calibration reference, DC gain, and offset. Appropriate constants are stored in nonvolatile memory. Calibration Specifications valid within 2 ye
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Software Table 12. Specification Value Comments Driver NI-FGEN 2.3 or later version. NI-FGEN is an — Software IVI-compliant driver that allows you to configure, control, and calibrate the NI 5412. NI-FGEN provides application programming interfaces for many development environments. Application NI-FGEN provides programming interfaces for the — Software following application development environments: LabVIEW ™ ™ LabWindows /CVI Measurement Studio Microsoft Visual C++ .NET Microsoft
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Environment NI PXI-5412 Environment Note To ensure that the NI PXI-5412 cools effectively, follow the guidelines in the Maintain Forced-Air Cooling Note to Users included in the NI 5412 kit. The NI PXI-5412 is intended for indoor use only. Table 13. Specifications Value Comments Operating 0 ºC to +55 ºC in all NI PXI chassis except the following: — Temperature 0 ºC to +45 ºC when installed in an NI PXI-101x or NI PXI-1000B chassis. Meets IEC-60068-2-1 and IEC-60068-2-2. Storage –25 ºC to +8
