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Table of Contents Chapter 1: Introduction................................................................................................. 5 Specifications ............................................................................................................ 7 Figure 1-1: Card D or H Block Diagram .................................................................. 8 Chapter 2: Installation................................................................................................. 1
Chapter 1: Introduction Features • 24 Bits of Digital Input/Output. • All 24 I/O Lines Buffered on the Card. • I/O Buffers Can Be Tri-stated under Program Control. • Four and Eight Bit Ports Independently Selectable for I/O. • Pull-Ups on I/O Lines. Pull Down resistors may be installed at the factory (**per port 8 bit**) • Resettable fused +5V Supply Available to the User. • "H" version compatible with Industry Standard I/O Racks. • Three optional i8254 type (**9 16-bit conver
output use according to direction assignment from a control register in the PPI. Further, if a jumper is properly placed on the card, the tristate buffers may be enabled/disabled under program control. (See the Option Selection section to follow.) I/O wiring connections for the H card are via a 50-pin connector on the back plate of the card. Flat insulation-displacement ribbon cables can be used to connect these cards to termination panels and relay output cards. Also, the 50-pin connec
Specifications Digital Inputs (TTL Compatible) • Logic High: 2.0 to 5.0 VDC • Logic Low: -0.5 to +0.8 VDC • Load: ±20 μA Digital Outputs • Logic High: 2.0 VDC min., source 32 ma • Logic Low: 0.55 VDC max., sink 64 ma Optional Counter/Timers • Type: 82C54 programmable interval counters (up to three) • Output drive: Source 2.5 mA, sink 24 mA • Input Gate: TTL/CMOS compatible • Clock: On-board, 1 MHz crystal-controlled oscillator • Active Count Edge: Neg
Figure 1-1: Card D or H Block Diagram Manual PCI-DIO-24DH 8
Optional Counter/Timers These cards have options to include one, two, or three 82C54 counter(s) that each include three 16-bit counter/timers factory configured in an optimal module for use as event counters, frequency output, pulse width, and frequency measurement. See the Block Diagram which shows one 82C54 counter. If your card has one or more of these optional counters, an -S01, -S02, or -S03 is appended to the model number for one, two, or three counters respectively. For example, a 24-
Chapter 2: Installation A printed Quick-Start Guide (QSG) is packed with the card for your convenience. If you’ve already performed the steps from the QSG, you may find this chapter to be redundant and may skip forward to begin developing your application. The software provided with this card is on CD and must be installed onto your hard disk prior to use. To do this, perform the following steps as appropriate for your operating system. Configure Card Options via Jumper Selection
Hardware Installation 1. Make sure to set switches and jumpers from either the Option Selection section of this manual or from the suggestions of SETUP.EXE. 2. Do not install card into the computer until the software has been fully installed. 3. Turn OFF computer power AND unplug AC power from the system. 4. Remove the computer cover. 5. Carefully install the card in an available 5V or 3.3V PCI expansion slot (you may need to remove a backplate first). 6. Inspect for proper fit of the
Chapter 3: Option Selection Refer to the setup programs on the CD provided with the card. Also, refer to the Block Diagram and the Option Selection Map when reading this section of the manual. Buffer Mode Jumper A means of enabling or disabling (tristating) the 74ABT245B input/output buffers under program control is provided at the jumper position labeled TST/BEN. When the jumper is in the BEN (Buffer Enable) position, the I/O buffers are always enabled. When the jumper is in the TST
4.8" IRQD IRQT TST INTEN BEN INT EXT INTSEL0 Figure 3-1: Option Selection Map version D Figure 3-2: Option Selection Map version H Manual PCI-DIO-24DH 13 3.9"
Chapter 4: Address Selection These cards use one address space and occupy sixteen I/O locations. The S03 (which has 3 counters) version takes up 32 I/O locations. PCI architecture is Plug-and-Play. This means that the BIOS or Operating System determines the resources assigned to PCI cards rather than the user selecting those resources with switches or jumpers. As a result, you cannot set or change the card's base address or IRQ level. You can only determine what the system has assigne
Chapter 5: Software There are sample programs provided with the card in C, Pascal, QuickBASIC, and several Windows languages. DOS samples are located in the DOS directory and Windows samples are located in the WIN32 directory. The following paragraphs describe the setup program and the 16- and 32-bit utility drivers. SETUP.EXE This program is supplied in the root or base directory as a tool for you to use in configuring jumpers on the card. It is menu-driven and provides pictures of
Chapter 6: Programming These cards are I/O-mapped devices that are easily configured from any language and any language can easily perform digital I/O through the card's ports. This is especially true if the form of the data is byte or word wide. All references to the I/O ports would be in absolute port addressing. Developing Your Application Software If you wish to gain a better understanding of the programs on diskette, then the information in the following paragraphs will be of i
These cards use an 8255-5 PPI to provide a total of 24 bits input/output capability. The card is designed to use the PPI in Mode 0 wherein: a. There are two 8-bit groups (A and B) and two 4-bit groups (C Hi and C Lo). b. Any port can be configured as an input or an output. c. Outputs are latched. d. Inputs are not latched. The PPI contains a Control Register. This write-only, 8-bit register is used to set the mode and direction of the ports. At Power-Up or Reset, all I/O lines are s
c. Now, if any of the ports are to be set as outputs, you may set the values to that port with the outputs still in the tristate condition. (If all ports are to be set as inputs, this step is not necessary.) d. If data bit D7 is low when the control byte is written, ONLY the associated buffer controller is addressed. If, for example, a control byte of hex 80 has been sent as previously described, and the data to be output are correct, and it is now desired to open the three groups, then i
Programming Example (C) The following program fragment in C language illustrates the foregoing: const BASE_ADDRESS 0x300; outportb(BASE_ADDRESS +3, 0x89); /*This instruction sets the mode to Mode 0, ports A and B as output, and port C as input. Since bit D7 is high, the output buffers are set to tristate condition. See item b. above.*/ outportb(BASE_ADDRESS,0); outportb(BASE_ADDRESS+1,0); /*These instructions set the initial state of ports A and B to all zeroes. Port C is not se
Enabling/Disabling I/O Buffers When using the tristate mode (Jumper in the TST position), the method to disable the I/O buffers involved writing a control word to the Control Register at Base Address +3. This control word was required to have bit D7 (the most significant bit) set. That meant that the PPI translated it as an "active mode set" and reset the output data latches to "zero" on all output ports and the output buffers were disabled. However, if the buffers are to be enabled at a
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