Summary of the content on the page No. 1
CY7C1350G
4-Mbit (128K x 36) Pipelined SRAM
with NoBL™ Architecture
[1]
Features Functional Description
• Pin compatible and functionally equivalent to ZBT™ The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined
devices Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
• Internally self-timed output buffer control to eliminate
wait states. The CY7C1350G is equipped with the advanced
the need to use OE
No Bus Latency™ (NoBL
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CY7C1350G Selection Guide 250 MHz 200 MHz 166 MHz 133 MHz 100 MHz Unit Maximum Access Time 2.6 2.8 3.5 4.0 4.5 ns Maximum Operating Current 325 265 240 225 205 mA Maximum CMOS Standby Current 40 40 40 40 40 mA Pin Configurations 100-Pin TQFP Pinout DQP 1 C 80 DQP B DQ 2 C 79 DQ B 3 DQ C 78 DQ B 4 V 77 V DDQ DDQ 5 V 76 V SS SS DQ 6 75 C DQ BYTE B B BYTE C DQ 7 74 C DQ B DQ 8 C 73 DQ B DQ 9 C 72 DQ B 10 V SS 71 V SS 11 V DDQ 70 V DDQ 12 DQ 69 DQ C B 13 DQ 68 C DQ B CY7C1350G NC 14 67 V SS V
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CY7C1350G Pin Configurations (continued) 119-Ball BGA Pinout 1 23 4 5 6 7 V AA NC/18M A A V A DDQ DDQ NC/576M CE A A NC B 2 ADV/LD CE 3 C NC/1G A A V AA NC DD DQ DQP V NC V DQP DQ D C C SS SS B B DQ DQ V V DQ DQ E CE C C SS SS B B 1 F V DQ V V DQ V OE DDQ C SS SS B DDQ DQ DQ BW NC/9M BW DQ DQ G C C C B B B H DQ DQ V V DQ DQ WE C C SS SS B B J V V V V V V V DDQ DD SS DD SS DD DDQ DQ DQ V CLK V DQ DQ K D D SS SS A A L DQ DQ BW NC DQ DQ BW D D D A A A V DQ V V DQ V M DDQ D SS CEN SS A DDQ N DQ D
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CY7C1350G Pin Definitions (continued) Name I/O Description ZZ Input- ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition Asynchronous with data integrity preserved.During normal operation, this pin has to be low or left floating. ZZ pin has an internal pull-down. DQs I/O- Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered Synchronous by the rising edge of CLK. As outputs, they deliver the data c
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CY7C1350G On the subsequent clock rise the data lines are automatically ignored and the burst counter is incremented. The correct tri-stated regardless of the state of the OE input signal. This BW inputs must be driven in each cycle of the burst write [A:D] allows the external logic to present the data on DQs and in order to write the correct bytes of data. DQP . In addition, the address for the subsequent access [A:D] Sleep Mode (Read/Write/Deselect) is latched into the Address Register T
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CY7C1350G [2, 3, 4, 5, 6, 7, 8] Truth Table (continued) Operation Address Used CE ZZ ADV/LD WE BW OE CEN CLK DQ x NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-State WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-State IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H — SNOOZE MODE None X H X X X X X X Tri-State [2, 3, 9] Partial Truth Table for Read/Write Function WE BW BW BW BW D C B A Read H X X X X Write − No bytes written L H H H H Write Byte A − (DQ and DQP) L HHH L
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CY7C1350G DC Input Voltage ....................................... −0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage........................................... > 2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ..................................... −65°C to +150°C Latch-up Current.........................................
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CY7C1350G [10, 11] Electrical Characteristics Over the Operating Range (continued) Parameter Description Test Conditions Min. Max. Unit I Automatic CE V = Max, Device Deselected, or 4-ns cycle, 250 MHz 105 mA SB3 DD Power-Down V ≤ 0.3V or V > V – 0.3V IN IN DDQ 5-ns cycle, 200 MHz 95 mA Current—CMOS f = f = 1/t MAX CYC 6-ns cycle, 166 MHz 85 mA Inputs 7.5-ns cycle, 133 MHz 75 mA 10-ns cycle, 100 MHz 65 mA I Automatic CE V = Max, Device Deselected, All speeds 45 mA SB4 DD Power-Down V ≥ V or
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CY7C1350G [17, 18] Switching Characteristics Over the Operating Range –250 –200 –166 –133 –100 Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit [13] t V (typical) to the first Access 1 1 1 1 1 ms POWER DD Clock t Clock Cycle Time 4.0 5.0 6.0 7.5 10 ns CYC t Clock HIGH 1.7 2.0 2.5 3.0 3.5 ns CH t Clock LOW 1.7 2.0 2.5 3.0 3.5 ns CL Output Times t Data Output Valid After CLK Rise 2.6 2.8 3.5 4.0 4.5 ns CO t Data Output Hold After CLK Rise 1.0 1.0 1.5 1.5 1.5 ns DOH [
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CY7C1350G Switching Waveforms [19, 20, 21] Read/Write Timing 123 456789 10 t CYC CLK t t t t CENS CENH CL CH CEN t t CES CEH CE ADV/LD WE BW[A:D] A1 A2 A3 A4 A5 A6 A7 ADDRESS t CO t t t DS DH t t t DOH t t CLZ OEV CHZ AS AH Data D(A1) D(A2) D(A2+1) Q(A3) Q(A4) Q(A4+1) D(A5) Q(A6) In-Out (DQ) t OEHZ t DOH t OELZ OE WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D(A1) D(A2) WRITE Q(A3) Q(A4) READ D(A5) Q(A6) D(A7) D(A2+1) Q(A4+1) DON’T CARE UNDEFINED Notes: For this waveform ZZ is
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CY7C1350G Switching Waveforms (continued) [19, 20, 22] NOP, STALL, and DESELECT Cycles 123 456 789 10 CLK CEN CE ADV/LD WE BW[A:D] A1 A2 A3 A4 A5 ADDRESS t CHZ D(A4) D(A1) Q(A2) Q(A3) Q(A5) Data In-Out (DQ) WRITE READ STALL READ WRITE STALL NOP READ DESELECT CONTINUE D(A1) Q(A2) Q(A3) D(A4) Q(A5) DESELECT DON’T CARE UNDEFINED [23, 24] ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 22. The IGNO
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CY7C1350G Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed Package Operating (MHz) Ordering Code Diagram Package Type Range 100 CY7C1350G-100AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1350G-100BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1350G-100BGXC 119-ball Ball Grid Array (14 x 22 x 2.4
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CY7C1350G Package Diagrams 100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 100 81 1 80 0.30±0.08 0.65 12°±1° SEE DETAIL A TYP. (8X) 30 51 31 50 0.20 MAX. 1.60 MAX. R 0.08 MIN. 0° MIN. 0.20 MAX. SEATING PLANE STAND-OFF 0.05 MIN. NOTE: 0.25 0.15 MAX. 1. JEDEC STD REF MS-026 GAUGE PLANE 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE R 0.08 MIN. BODY LENGTH DIMENSIONS ARE MAX PLA
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CY7C1350G Package Diagrams (continued) 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) Ø0.05 M C Ø0.25MCAB A1 CORNER Ø0.75±0.15(119X) Ø1.00(3X) REF. 16 237 4 5 7 65 43 21 A A B B C C D D E E F F G G H H J J K K L L M M N N P P R R T T U U 1.27 0.70 REF. A 3.81 12.00 7.62 B 14.00±0.20 0.15(4X) 30° TYP. 51-85115-*B SEATING PLANE C ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All product and company names mentione
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CY7C1350G Document History Page Document Title: CY7C1350G 4-Mbit (128K x 36) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05524 Issue Orig. of REV. ECN NO. Date Change Description of Change ** 224380 See ECN RKF New data sheet *A 276690 See ECN VBL Changed TQFP pkg to lead-free TQFP in Ordering Info section Added comment of BG lead-free package availability *B 332895 See ECN SYT Converted from Preliminary to Final Removed 225 MHz and 100 MHz speed grades Address Expansion balls
