Cypress FLEx36 CYD18S36V user manual

User manual for the device Cypress FLEx36 CYD18S36V

Device: Cypress FLEx36 CYD18S36V
Category: Computer Hardware
Manufacturer: Cypress
Size: 0.78 MB
Added : 10/17/2014
Number of pages: 28
Print the manual

Download

How to use this site?

Our goal is to provide you with a quick access to the content of the user manual for Cypress FLEx36 CYD18S36V. Using the online preview, you can quickly view the contents and go to the page where you will find the solution to your problem with Cypress FLEx36 CYD18S36V.

For your convenience

If looking through the Cypress FLEx36 CYD18S36V user manual directly on this website is not convenient for you, there are two possible solutions:

  • Full Screen Viewing - to easily view the user manual (without downloading it to your computer), you can use full-screen viewing mode. To start viewing the user manual Cypress FLEx36 CYD18S36V on full screen, use the button Fullscreen.
  • Downloading to your computer - You can also download the user manual Cypress FLEx36 CYD18S36V to your computer and keep it in your files. However, if you do not want to take up too much of your disk space, you can always download it in the future from ManualsBase.
Cypress FLEx36 CYD18S36V User manual - Online PDF
Advertisement
« Page 1 of 28 »
Advertisement
Print version

Many people prefer to read the documents not on the screen, but in the printed version. The option to print the manual has also been provided, and you can use it by clicking the link above - Print the manual. You do not have to print the entire manual Cypress FLEx36 CYD18S36V but the selected pages only. paper.

Summaries

Below you will find previews of the content of the user manuals presented on the following pages to Cypress FLEx36 CYD18S36V. If you want to quickly view the content of pages found on the following pages of the manual, you can use them.

Abstracts of contents
Summary of the content on the page No. 1

CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
FLEx36™ 3.3V 32K/64K/128K/256K/512 x 36
Synchronous Dual-Port RAM
Features Functional Description
■ True dual-ported memory cells that enable simultaneous The FLEx36™ family includes 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit, and
access of the same memory location 18-Mbit pipelined, synchronous, true dual-port static RAMs that
are high speed, low power 3.3V CMOS. Two ports are provided,
■ Synchronous pipelined operation
permitting independent, simulta

Summary of the content on the page No. 2

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V [1] Logic Block Diagram FTSEL FTSEL L R CONFIG Block CONFIG Block PORTSTD[1:0] PORTSTD[1:0] L R DQ [35:0] DQ [35:0] R L BE [3:0] BE [3:0] R L CE0 CE0 L R IO IO CE1 CE1 R L Control Control OE OE R L R/W R/W R L Dual Ported Array Arbitration Logic BUSY L BUSY R A [18:0] A [18:0] L R CNT/MSK CNT/MSK L R ADS ADS L R CNTEN CNTEN L R Address & Address & CNTRST CNTRST L R Counter Logic Counter Logic RET RET L R CNTINT L CNTINT R C L C R WRP L WRP R

Summary of the content on the page No. 3

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Pin Configurations Figure 1. Pin Diagram - 256-Ball FBGA (Top View) CYD01S36V/CYD02S36V/36VA/CYD04S36V/CYD09S36V/CYD18S36V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A DQ32L DQ30L DQ28L DQ26L DQ24L DQ22L DQ20L DQ18L DQ18R DQ20R DQ22R DQ24R DQ26R DQ28R DQ30R DQ32R B DQ33L DQ31L DQ29L DQ27L DQ25L DQ23L DQ21L DQ19L DQ19R DQ21R DQ23R DQ25R DQ27R DQ29R DQ31R DQ33R RETL NC NC REVL TRST NC NC NC

Summary of the content on the page No. 4

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Pin Definitions Left Port Right Port Description A –A A –A Address Inputs. 0L 18L 0R 18R BE –BE BE –BE Byte Enable Inputs. Asserting these signals enables Read and Write operations to the 0L 3L 0R 3R corresponding bytes of the memory array. [2,5] [2,5] BUSY BUSY Port Busy Output. When the collision is detected, a BUSY is asserted. L R C C Input Clock Signal. L R [11] [11] CE0 CE0 Active Low Chip Enable Input. L R [10] [10] CE1 CE1 Acti

Summary of the content on the page No. 5

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Master Reset Address Counter and Mask Register [19] Operations The FLEx36 family devices undergo a complete reset by taking its MRST input LOW. The MRST input can switch asynchro- This section describes the features only apply to 1Mbit, 2 Mbit, nously to the clocks. An MRST initializes the internal burst 4 Mbit and 9 Mbit devices. It does not apply to 18Mbit device. counters to zero, and the counter mask registers to all ones Each port of t

Summary of the content on the page No. 6

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Counter enable (CNTEN) inputs are provided to stall the Counter Reset Operation operation of the address input and use the internal address All unmasked bits of the counter and mirror registers are reset to generated by the internal counter for fast, interleaved memory “0.” All masked bits remain unchanged. A Mask Reset followed applications. A port’s burst counter is loaded when the port’s by a Counter Reset resets the counter and mirror re

Summary of the content on the page No. 7

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V after the next rising edge of the port’s clock. If address readback Counter Increment Operation occurs while the port is enabled (CE0 LOW and CE1 HIGH), the Once the address counter register is initially loaded with an data lines (DQs) are three-stated. Figure 2 on page 8 shows a external address, the counter can internally increment the block diagram of the operation. address value, potentially addressing the entire memory array. Only the u

Summary of the content on the page No. 8

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V [1] Figure 2. Counter, Mask, and Mirror Logic Block Diagram CNT/MSK CNTEN Decode ADS Logic CNTRST MRST Bidirectional Mask Address Register Lines Counter/ Address RAM Address Decode Array Register CLK Load/Increment From 17 Address Mirror Counter Lines To Readback 1 1 and Address 0 Decode 0 From 17 Increment Mask Logic Wrap 17 Register 17 17 From Mask Bit 0 17 From +1 Wrap Counter Wrap 1 Detect 0 +2 17 1 To Counter 0 Document Number

Summary of the content on the page No. 9

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V [1, 22] Figure 3. Programmable Counter-Mask Register Operation CNTINT Example: Load Counter-Mask H 0 0 0s01 11 1 1 1 Register = 3F 16 15 6 5 4 3 2 1 0 Mask 2 2 2 2 2 2 2 2 2 Register Masked Address Unmasked Address bit-0 Load Address H X X Xs X0 00 1 0 0 Counter = 8 16 15 6 5 4 3 2 1 0 2 2 2 2 2 2 2 2 2 Address Counter Max bit-0 Address L X X Xs X1 11 1 1 1 Register 16 15 6 5 4 3 2 1 0 2 2 2 2 2 2 2 2 2 Max + 1 Address H X X XsX0 00 1 0 0

Summary of the content on the page No. 10

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Figure 4. Scan Chain for 18-Mbit Device TDO TDO TDO D4 D2 TDI TDI TDO TDO D3 D1 TDI TDI TDI Figure 5. Scan Chain for 9-Mbit Device TDO TDO D2 TDI TDO D1 TDI TDI Table 4. Identification Register Definitions Instruction Field Value Description Revision Number (31:28) 0h Reserved for version number. Cypress Device ID (27:12) C002h Defines Cypress part number for CYD04S36V, CYD09S36V and CYD18S36V C001h Defines Cypress part number for CY

Summary of the content on the page No. 11

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Table 6. Instruction Identification Codes Instruction Code Description EXTEST 0000 Captures the Input/Output ring contents. Places the BSR between the TDI and TDO. BYPASS 1111 Places the BYR between TDI and TDO. IDCODE 1011 Loads the IDR with the vendor ID code and places the register between TDI and TDO. HIGHZ 0111 Places BYR between TDI and TDO. Forces all device output drivers to a High-Z state. CLAMP 0100 Controls boundary to 1/0. Pla

Summary of the content on the page No. 12

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage........................................... > 2000V [25] Exceeding maximum ratings may shorten the useful life of the (JEDEC JESD22-A114-2000B) device. User guidelines are not tested. Latch-up Current..................................................... > 200 mA Storage Temperature.................................. –65°C to +150°C Ope

Summary of the content on the page No. 13

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Figure 6. AC Test Load and Waveforms 3.3V Z = 50 Ω R = 50 Ω 0 OUTPUT R1 = 590 Ω OUTPUT C = 10 pF C = 5 pF V = 1.5V R2 = 435 Ω TH (a) Normal Load (Load 1) (b) Three-state Delay (Load 2) 3.0V 90% 90% 10% 10% ALL INPUT PULSES Vss <2ns <2ns Switching Characteristics Over the Operating Range -167 -133 -100 CYD01S36V CYD01S36V CYD02S36V/ CYD02S36V Parameter Description CYD02S36VA CYD18S36V CYD18S36V Unit CYD04S36V CYD04S36V CYD09S36V CYD09S36V Mi

Summary of the content on the page No. 14

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Switching Characteristics Over the Operating Range (continued) -167 -133 -100 CYD01S36V CYD01S36V CYD02S36V/ CYD02S36V Parameter Description CYD02S36VA CYD18S36V CYD18S36V Unit CYD04S36V CYD04S36V CYD09S36V CYD09S36V Min Max Min Max Min Max Min Max t CNT/MSK Hold Time 0.6 0.6 NA NA ns HCM t Output Enable to Data Valid 4.4 4.4 5.5 5.5 ns OE [31, 32] t OE to Low Z 0 0 0 0 ns OLZ [31, 32] t OE to High Z 0 4.0 0 4.4 0 5.5 0 5.5 ns OHZ t Clock to

Summary of the content on the page No. 15

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V JTAG Switching Waveform t t TH TL Test Clock t TCYC TCK t TMSS t TMSH Test Mode Select TMS t TDIS t TDIH Test Data-In TDI Test Data-Out TDO t TDOV t TDOX Switching Waveforms Figure 7. Master Reset t RS MRST t ALL RSF ADDRESS/ DATA t LINES RSS t RSR ALL OTHER INACTIVE ACTIVE INPUTS TMS t RSINT CNTINT INT TDO Document Number: 38-06076 Rev. *G Page 15 of 28 [+] Feedback

Summary of the content on the page No. 16

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Switching Waveforms (continued) [14, 33, 34, 35, 36] Figure 8. Read Cycle t CYC2 t t CH2 CL2 CLK CE t t t t SC HC SC HC t SB t HB BE0–BE3 R/W t t SW HW t t SA HA ADDRESS A A A A n n+1 n+2 n+3 t 1 Latency t DC CD2 DATA OUT Q Q Q n n+1 n+2 t OHZ t t CKLZ OLZ OE t OE Notes 33. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge. 34. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK

Summary of the content on the page No. 17

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Switching Waveforms (continued) [37, 38] Figure 9. Bank Select Read t CYC2 t t CH2 CL2 CLK t t SA HA ADDRESS A A A A A (B1) 0 A 3 4 5 1 2 t t HC SC CE (B1) t t t t t t t CD2 HC CD2 CD2 CKHZ SC CKHZ Q Q Q 3 DATA 0 1 OUT(B1) t t SA HA t t t DC DC CKLZ A A A A ADDRESS A 0 A 3 4 5 (B2) 1 2 t t SC HC CE (B2) t t t t t CD2 CKHZ CD2 SC HC DATA OUT(B2) Q Q 4 2 t t CKLZ CKLZ [36, 39, 40, 41, 42] Figure 10. Read-to-Write-to-Read (OE = LOW) t CYC2

Summary of the content on the page No. 18

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Switching Waveforms (continued) [36, 39, 41, 42] Figure 11. Read-to-Write-to-Read (OE Controlled) t CYC2 t t CH2 CL2 CLK CE t t SC HC t t SW HW R/W t t SW HW A A A A A A n n+1 n+2 n+3 n+4 n+5 ADDRESS t t t t SA HA SD HD D DATA D IN n+2 n+3 t CD2 t CD2 DATA OUT Q Q n n+4 t OHZ OE READ WRITE READ [41] Figure 12. Read with Address Counter Advance t CYC2 t t CH2 CL2 CLK t t SA HA ADDRESS A n t t SAD HAD ADS t t SAD HAD CNTEN t t SCN HCN t t

Summary of the content on the page No. 19

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Switching Waveforms (continued) [42] Figure 13. Write with Address Counter Advance t CYC2 t t CH2 CL2 CLK t t SA HA A ADDRESS n INTERNAL A A A A A n n+1 n+2 n+3 n+4 ADDRESS t t SAD HAD ADS CNTEN t t SCN HCN D D D D D D DATA n n+1 n+1 n+2 n+3 n+4 IN t t SD HD WRITE EXTERNAL WRITE WITH WRITE COUNTER WRITE WITH COUNTER ADDRESS COUNTER HOLD Document Number: 38-06076 Rev. *G Page 19 of 28 [+] Feedback

Summary of the content on the page No. 20

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Switching Waveforms (continued) [43, 44] Figure 14. Counter Reset t CYC2 t t CH2 CL2 CLK t t SA HA A A A ADDRESS n m p INTERNAL A A 0 1 A A p x n m ADDRESS t t SW HW R/W ADS CNTEN t t HRST SRST CNTRST t t SD HD DATA D IN 0 t t CD2 CD2 [45] DATA Q OUT Q Q 0 1 n t CKLZ COUNTER WRITE READ READ READ READ ADDRESS A RESET ADDRESS 0 ADDRESS 0 ADDRESS 1 ADDRESS A m n Notes 43. CE = BE0 – BE3 = LOW; CE = MRST = CNT/MSK = HIGH. 0 1 44. No dead cyc


Alternative user manuals
# User manual Category Download
1 Cypress CapSense CY8C20x36 User manual Computer Hardware 0
2 Cypress CY14B101L User manual Computer Hardware 0
3 Cypress CY14B101LA User manual Computer Hardware 0
4 Cypress CY14B104N User manual Computer Hardware 0
5 Cypress AutoStore STK14CA8 User manual Computer Hardware 0
6 Cypress CY14B101Q2 User manual Computer Hardware 0
7 Cypress CY14B104L User manual Computer Hardware 0
8 Cypress CY2048WAF User manual Computer Hardware 0
9 Cypress CY14B108L User manual Computer Hardware 0
10 Cypress 7C185-15 User manual Computer Hardware 0
11 Cypress CY14B104NA User manual Computer Hardware 0
12 Cypress CY14B104M User manual Computer Hardware 0
13 Cypress AutoStore STK17TA8 User manual Computer Hardware 0
14 Cypress CY62158E User manual Computer Hardware 0
15 Cypress CY14B256L User manual Computer Hardware 0
16 Sony MSAKIT-PC4A User manual Computer Hardware 2
17 Sony MRW62E-S1 2694866142 User manual Computer Hardware 5
18 Philips MATCH LINE 9596 User manual Computer Hardware 17
19 Sony 64GB SDHC Class 10 Memory Card Readers SF32UY User manual Computer Hardware 1
20 Philips PSC702 User manual Computer Hardware 1