Summary of the content on the page No. 1
®
CY62148BN MoBL
4-Mbit (512K x 8) Static RAM
Features Functional Description
• High Speed The CY62148BN is a high-performance CMOS static RAM
organized as 512K words by 8 bits. Easy memory expansion
—70 ns
is provided by an active LOW Chip Enable (CE), an active
• 4.5V–5.5V operation
LOW Output Enable (OE), and three-state drivers. This device
has an automatic power-down feature that reduces power
• Low active power
consumption by more than 99% when deselected.
— Typical active current: 2.5
Summary of the content on the page No. 2
® CY62148BN MoBL Pin Configuration Top View Top View SOIC Reverse TSOP II TSOP II GND I/O V 17 A 1 32 16 3 17 CC A I/O 31 2 15 18 I/O 16 2 A 15 4 I/O 19 I/O A 14 3 30 A 1 5 14 18 I/O A 13 20 I/O 0 12 4 29 WE 6 21 28 12 I/O A A 5 7 7 A 0 13 22 A A 27 11 6 1 CE 6 A 8 23 A A 26 10 10 A 2 A 5 7 9 A 24 9 OE 25 3 A 8 A 4 11 A A 25 8 11 4 A 24 9 3 OE A 26 7 A A 5 9 2 23 A 10 10 A 27 A 6 6 8 A 22 CE 1 11 A A 28 5 13 7 21 I/O A 12 7 0 A 12 29 4 WE I/O I/O 0 13 20 6 A A 30 14 3 18 I/O I/O 1 19 5 14 A A
Summary of the content on the page No. 3
® CY62148BN MoBL Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage...............................................2001V (Above which the useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015) lines, not tested.) Latch-Up Current..................................................... >200 mA Storage Temperature .................................–65°C to +150°C Ambient Temperature with Operating Range Power Applied
Summary of the content on the page No. 4
® CY62148BN MoBL [5] Switching Characteristics Over the Operating Range 62148BNLL-70 Parameter Description Min. Max. Unit READ CYCLE t Read Cycle Time 70 ns RC t Address to Data Valid 70 ns AA t Data Hold from Address Change 10 ns OHA t CE LOW to Data Valid 70 ns ACE t OE LOW to Data Valid 35 ns DOE [6] t OE LOW to Low Z 5 ns LZOE [6, 7] t OE HIGH to High Z 25 ns HZOE [6] t CE LOW to Low Z 10 ns LZCE [6, 7] t CE HIGH to High Z 25 ns HZCE t CE LOW to Power-Up 0 ns PU t CE HIGH to Power-Down 70
Summary of the content on the page No. 5
® CY62148BN MoBL Data Retention Characteristics (Over the Operating Range) [1] Parameter Description Conditions Min. Typ. Max. Unit V V for Data Retention 2.0 V DR CC I Data Retention Current Com’l LL No input may exceed 20 µA CCDR V + 0.3V CC Ind’l LL 20 µA V = V = 3.0V CC DR [4] t Chip Deselect to Data Retention Time CE > V – 0.3V 0 ns CDR CC V > V – 0.3V or [9] IN CC t Operation Recovery Time t ns R RC V < 0.3V IN Data Retention Waveform DATA RETENTION MODE 3.0V 3.0V V V > 2V DR CC t t CD
Summary of the content on the page No. 6
® CY62148BN MoBL Switching Waveforms (continued) [13] Write Cycle No. 1 (CE Controlled) t WC ADDRESS t SCE CE t SA t t AW HA t PWE WE t t SD HD DATA I/O DATA VALID [13, 14] Write Cycle No. 2 (WE Controlled, OE HIGH During Write) t WC ADDRESS t SCE CE t HZCE t t AW HA t t SA PWE WE OE t t SD HD DATA VALID DATA I/O IN NOTE 15 t HZOE Notes: 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 14. Data I/O is high-impedance if OE = V . IH 15. During
Summary of the content on the page No. 7
® CY62148BN MoBL Switching Waveforms (continued) [13, 14] Write Cycle No.3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE t HZCE t t AW HA t t SA PWE WE t t SD HD NOTE 15 DATAI/O DATA VALID t t LZWE HZWE Truth Table CE OE WE I/O –I/O Mode Power 0 7 H X X High Z Power-Down Standby (I ) SB L L H Data Out Read Active (I ) CC L X L Data In Write Active (I ) CC L H H High Z Selected, Outputs Disabled Active (I ) CC Ordering Information Speed Package Operating (ns) Ordering Code Diagram Package Type
Summary of the content on the page No. 8
® CY62148BN MoBL Package Diagrams 32 LD (450 Mil) SOIC 32-lead (450-Mil) Molded SOIC (51-85081) 16 1 0.546[13.868] 0.566[14.376] 0.440[11.176] MIN. DIMENSIONS IN INCHES[MM] 0.450[11.430] MAX. PACKAGE WEIGHT 1.42gms PART # S32.45 STANDARD PKG. SZ32.45 LEAD FREE PKG. 17 32 0.793[20.142] 0.006[0.152] 0.817[20.751] 0.012[0.304] 0.101[2.565] 0.118[2.997] 0.111[2.819] MAX. 0.004[0.102] 0.047[1.193] 0.004[0.102] 0.063[1.600] 0.050[1.270] MIN. 0.023[0.584] BSC. 0.039[0.990] 0.014[0.355] 0.020[0.508] S
Summary of the content on the page No. 9
® CY62148BN MoBL Package Diagrams (continued) 32-lead Reverse Thin Small Outline Package Type II (51-85138) 51-85138-** More Battery Life is a trademark, and MoBL is a registered trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06517 Rev. *A Page 9 of 10 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semicond
Summary of the content on the page No. 10
® CY62148BN MoBL Document History Page ® Document Title: CY62148BN MoBL 4-Mbit (512K x 8) Static RAM Document Number: 001-06517 Issue Orig. of REV. ECN NO. Date Change Description of Change ** 426504 See ECN NXR New Data Sheet *A 485639 See ECN VKN Corrected the typo in the Array size in the Logic Block Diagram Document #: 001-06517 Rev. *A Page 10 of 10 [+] Feedback
