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STK12C68
64 Kbit (8K x 8) AutoStore nvSRAM
Features Functional Description
■ 25 ns, 35 ns, and 45 ns access times The Cypress STK12C68 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
■ Hands off automatic STORE on power down with external 68
elements incorporate QuantumTrap technology producing the
µF capacitor
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
■ STORE to Quantu
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STK12C68 Pin Configurations Figure 1. 28-Pin SOIC/DIP and LLC Pin Definitions Pin Name Alt IO Type Description A –A Input Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM. 0 12 DQ -DQ Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation. 0 7 Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO WE W pins is written to the specific address location. Input Chip Enable Input, Active LOW. When LO
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STK12C68 During normal operation, the device draws current from V to Device Operation CC charge a capacitor connected to the V pin. This stored CAP charge is used by the chip to perform a single STORE operation. The STK12C68 nvSRAM is made up of two functional compo- If the voltage on the V pin drops below V , the part nents paired in the same physical cell. These are an SRAM CC SWITCH automatically disconnects the V pin from V . A STORE memory cell and a nonvolatile QuantumTrap cell. The SRAM C
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STK12C68 Figure 3. AutoStore Inhibit Mode During any STORE operation, regardless of how it is initiated, the STK12C68 continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the STK12C68 remains disabled until the HSB pin returns HIGH. If HSB is not used, it is left unconnected. Hardware RECALL (Power Up) During power up or after any low power condition (V < CC V ), an internal RECALL request is latc
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STK12C68 3. Read address 0x0AAA, Valid READ ■ The V level CC 4. Read address 0x1FFF, Valid READ ■ IO loading Figure 4. Current Versus Cycle Time (Read) 5. Read address 0x10F0, Valid READ 6. Read address 0x0F0E, Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the t cycle time, the SRAM is again RECALL ready for Read and Write operations. The RECALL operation does not alt
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STK12C68 manufacturing test to ensure these system routines work Best Practices consistently. nvSRAM products have been used effectively for over 15 years. ■ Power up boot firmware routines should rewrite the nvSRAM While ease-of-use is one of the product’s main system values, into the desired state. While the nvSRAM is shipped in a preset experience gained working with hundreds of applications has state, best practice is to again rewrite the nvSRAM into the resulted in the following suggest
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STK12C68 Voltage on DQ or HSB .......................–0.5V to Vcc + 0.5V Maximum Ratings 0-7 Power Dissipation.......................................................... 1.0W Exceeding maximum ratings may shorten the useful life of the DC output Current (1 output at a time, 1s duration) .... 15 mA device. These user guidelines are not tested. Storage Temperature ................................. –65 °C to +150 °C Operating Range Temperature under Bias ............................. –55 °C to +125
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STK12C68 Data Retention and Endurance Parameter Description Min Unit DATA Data Retention 100 Years R NV Nonvolatile STORE Operations 1,000 K C Capacitance [6] In the following table, the capacitance parameters are listed. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25 °C, f = 1 MHz, 8pF IN A V = 0 to 3.0 V CC C Output Capacitance 7pF OUT Thermal Resistance [6] In the following table, the thermal resistance parameters are listed. 28-PDIP 28-PDIP Parameter Description T
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STK12C68 AC Switching Characteristics SRAM Read Cycle Parameter 25 ns 35 ns 45 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameter t t Chip Enable Access Time 25 35 45 ns ACE ELQV [7] t t t Read Cycle Time 25 35 45 ns RC AVAV, ELEH [8] t t Address Access Time 25 35 45 ns AA AVQV t t Output Enable to Data Valid 10 15 20 ns DOE GLQV [8] t t Output Hold After Address Change 5 5 5 ns OHA AXQX [9] t t Chip Enable to Output Active 5 5 5 ns LZCE ELQX [9] t t Chip Disable to Output Inact
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STK12C68 SRAM Write Cycle Parameter 25 ns 35 ns 45 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameter t t Write Cycle Time 25 35 45 ns WC AVAV t t t Write Pulse Width 20 25 30 ns PWE WLWH, WLEH t t t Chip Enable To End of Write 20 25 30 ns SCE ELWH, ELEH t t t Data Setup to End of Write 10 12 15 ns SD DVWH, DVEH t t t Data Hold After End of Write 0 0 0 ns HD WHDX, EHDX t t t Address Setup to End of Write 20 25 30 ns AW AVWH, AVEH t t t Address Setup to Start of Write 0 0 0 ns SA
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STK12C68 AutoStore or Power Up RECALL STK12C68 Parameter Alt Description Unit Min Max [13] t t Power up RECALL Duration 550 μs HRECALL RESTORE [14, 15, 16] t t STORE Cycle Duration 10 ms STORE HLHZ [9, 15] t t t Time Allowed to Complete SRAM Cycle 1 μs DELAY HLQZ , BLQZ V Low Voltage Trigger Level 4.0 4.5 V SWITCH V Low Voltage Reset Level 3.9 V RESET t V Rise Time 150 μs VCCRISE CC [11] t Low Voltage Trigger (V ) to HSB Low 300 ns VSBL SWITCH Switching Waveform Figure 11. AutoStore/Power Up
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STK12C68 Software Controlled STORE/RECALL Cycle [18] The software controlled STORE/RECALL cycle follows. 25 ns 35 ns 45 ns Parameter Alt Description Unit Min Max Min Max Min Max [14] t t STORE/RECALL Initiation Cycle Time 25 35 45 ns RC AVAV [17] t t Address Setup Time 0 0 0 ns SA AVEL [17] t t Clock Pulse Width 20 25 30 ns CW ELEH [17] t t Address Hold Time 20 20 20 ns HACE ELAX RECALL Duration 20 20 20 μs t RECALL Switching Waveform [18] Figure 12. CE Controlled Software STORE/RECALL Cycle
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STK12C68 Hardware STORE Cycle STK12C68 Parameter Alt Description Unit Min Max [9, 14] t t STORE Cycle Duration 10 ms STORE HLHZ [14, 19] t t t Hardware STORE High to Inhibit Off 700 ns DHSB RECOVER, HHQX t t Hardware STORE Pulse Width 15 ns PHSB HLHX t Hardware STORE Low to STORE Busy 300 ns HLBL Switching Waveform Figure 13. Hardware STORE Cycle Note 19. t is only applicable after t is complete. DHSB STORE Document Number: 001-51027 Rev. ** Page 13 of 20 [+] Feedback
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STK12C68 Part Numbering nomenclature STK12C68 - S F 45 I TR Packaging Option: TR = Tape and Reel Blank = Tube Temperature Range: C - Commercial (0 to 70°C) I - Industrial (-40 to 85°C) Speed: 25 - 25 ns 35 - 35 ns 45 - 45 ns Lead Finish F = 100% Sn (Matte Tin) Package: S = Plastic 28-pin 330 mil SOIC P = Plastic 28-pin 300 mil DIP W = Plastic 28-pin 600 mil DIP C = Ceramic 28-pin 300 mil DIP L = Ceramic 28-pin LLC Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Oper
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STK12C68 Ordering Information (continued) Speed (ns) Ordering Code Package Diagram Package Type Operating Range 45 STK12C68-SF45TR 001-85058 28-pin SOIC (330 mil) Commercial STK12C68-SF45 001-85058 28-pin SOIC (330 mil) STK12C68-PF45 001-85014 28-pin PDIP (300 mil) STK12C68-WF45 001-85017 28-pin PDIP (600 mil) STK12C68-C45 001-51695 28-pin CDIP (300 mil) STK12C68-L45 001-51696 28-pin LCC (350 mil) STK12C68-SF45ITR 001-85058 28-pin SOIC (330 mil) Industrial STK12C68-SF45I 001-85058 28-pin SOIC (3
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STK12C68 Package Diagrams Figure 14. 28-Pin (330 Mil) SOIC (51-85058) 51-85058 *A Figure 15. 28-Pin (300 Mil) PDIP (51-85014) 51-85014 *D Document Number: 001-51027 Rev. ** Page 16 of 20 [+] Feedback
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STK12C68 Package Diagrams (continued) Figure 16. 28-Pin (600 Mil) PDIP (51-85017) 51-85017 *B Document Number: 001-51027 Rev. ** Page 17 of 20 [+] Feedback
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STK12C68 Package Diagrams (continued) Figure 17. 28-Pin (300 Mil) Side Braze DIL (001-51695) 001-51695 ** Document Number: 001-51027 Rev. ** Page 18 of 20 [+] Feedback
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STK12C68 Package Diagrams (continued) Figure 18. 28-Pad (350 Mil) LCC (001-51696) 1. ALL DIMENSION ARE IN INCHES AND MILLIMETERS [MIN/MAX] 2. JEDEC 95 OUTLINE# MO-041 3. PACKAGE WEIGHT : TBD 001-51696 ** Document Number: 001-51027 Rev. ** Page 19 of 20 [+] Feedback
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STK12C68 Document History Page Document Title: STK12C68 64 Kbit (8K x 8) AutoStore nvSRAM Document Number: 001-51027 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 2606744 GVCH 01/30/2009 New data sheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC
