Summary of the content on the page No. 1
DATA SHEET
MOS INTEGRATED CIRCUIT
μPD17062
4-BIT SINGLE-CHIP MICROCONTROLLER CONTAINING PLL FREQUENCY
SYNTHESIZER AND IMAGE DISPLAY CONTROLLER
The μPD17062 is a 4-bit CMOS microcontroller for digital tuning systems. The single-chip device
incorporates an image display controller enabling a range of different displays, together with a PLL frequency
synthesizer.
The CPU has six main functions: 4-bit parallel addition, logic operation, multiple bit test, carry-flag set/
reset, powerful interrupt,
Summary of the content on the page No. 2
μPD17062 ORDERING INFORMATION Part number Package μPD17062CU-××× 48-pin plastic shrink DIP (600 mil) μPD17062GC-××× 64-pin plastic QFP (14 × 14 mm) Remark ××× is the ROM code number. FUNCTION OVERVIEW Item Function ROM (program memory) capacity 3968 × 16 bits (masked ROM) CROM (character ROM) capacity 1920 × 16 bits (included in ROM) RAM (data memory) capacity 336 × 4 bits (including the area that can be used for VRAM) VRAM (video RAM) capacity 224 × 4 bits (included in RAM) Instruction execut
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μPD17062CU-××× μPD17062 PIN CONFIGURATION (TOP VIEW) 48-pin plastic shrink DIP (600 mil) P0C3 1 48 INTNC P0C2 2 47 P0A0/SDA P0C1 3 46 P0A1/SCL P0C0 4 45 P0A2/SCK P0D3/ADC5 5 44 P0A3/SO P0D2/ADC4 6 43 P0B0/SI P0D1/ADC3 7 42 P0B1 P0D0/ADC2 8 41 P0B2/TMIN PWM3 9 40 P0B3/HSCNT PWM2 10 39 ADC0 PWM1 11 38 P1C1 PWM0 12 37 P1C2 VDD 13 36 P1C3/ADC1 VCO 14 35 VSYNC EO 15 34 HSYNC GND 16 33 BLANK PSC 17 32 BLUE CE 18 31 GREEN XOUT 19 30 RED XIN 20 29 P1B0 P1A3 21 28 P1B1 P1A2 22 27 P1B2 P1A1 23 26 P1B3 P1A
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μPD17062 64-pin plastic QFP (14 × 14 mm) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P0D0/ADC2 1 48 POB2/TMIN PWM3 2 47 POB3/HSCNT PWM2 3 46 ADC0 PWM1 4 45 P1C1 NC 5 44 NC PWM0 6 43 P1C2 NC NC 7 42 NC 8 41 NC μPD17062GC-×××-3BE VDD 9 40 NC NC NC 10 39 11 38 VCO P1C3/ADC1 NC 12 37 NC EO VSYNC 13 36 NC 14 35 HSYNC GND 15 34 BLANK PSC 16 33 BLUE 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4 CE P0D1/ADC3 XOUT P0D2/ADC4 XIN P0D3/ADC5 P1A3 P0C0 P1A2 P0C1 NC P0C2 P1A1 P0C3 NC P1A0 NC NC GND INT
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μPD17062 BLOCK DIAGRAM VCO PSC PLL EO HSYNC PWM0 VSYNC PWM1 PWM PWM2 IDC RED PWM3 GREEN RF BLUE P1A0 RAM BLANK 336 × 4 bits P1A1 (Including VRAM) P1A P1A2 SYSREG P0A0/SDA P1A3 P0A1/SCL Serial P0A2/SCK P1B0 I/O P0A3/SO P1B1 P1B ALU P0B0/SI P1B2 P1B3 P0A P0C0 P0C1 P0C P0B1 P0B P0C2 P0B2/TMIN P0C3 ROM P0B3/HSCNT Hsync Counter 3968 × 16 bits Interrupt (Including CROM) INTNC Controller Timer Controller Instruction Decoder P0D0/ADC2 Program Counter P0D1/ADC3 CPU XIN P0D OSC P0D2/ADC4 Peripheral XOUT P
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μPD17062 CONTENTS 1. PINS ............................................................................................................................................. 11 1.1 PIN FUNCTIONS ............................................................................................................................. 11 1.2 EQUIVALENT CIRCUITS OF THE PINS ........................................................................................ 14 2. PROGRAM MEMORY (ROM) ..............................
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μPD17062 8.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP) ...................... 57 8.6 GENERAL-PURPOSE REGISTER POINTER (RP).......................................................................... 66 8.7 PROGRAM STATUS WORD (PSWORD) ...................................................................................... 66 9. REGISTER FILE (RF) ................................................................................................................... 67 9.1 IDCDMAEN (00H
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μPD17062 11.5 RETURNING CONTROL FROM INTERRUPT PROCESSING ROUTINE ..................................... 116 11.6 INTERRUPT PROCESSING ROUTINE ........................................................................................... 117 11.7 EXTERNAL INTERRUPTS (INTNC PIN, VSYNC PIN) ....................................................................... 121 11.8 INTERNAL INTERRUPT (TIMER, SERIAL INTERFACE) .............................................................. 123 11.9 MULTIPLE INTERRU
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μPD17062 17. D/A CONVERTER ....................................................................................................................... 217 17.1 PWM PINS ....................................................................................................................................... 217 18. PLL FREQUENCY SYNTHESIZER ............................................................................................. 219 18.1 PLL FREQUENCY SYNTHESIZER CONFIGURATION ......................
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μPD17062 23.5 PERIPHERAL HARDWARE REGISTER .......................................................................................... 286 23.6 OTHERS ........................................................................................................................................... 286 24. ELECTRICAL CHARACTERISTICS ............................................................................................. 287 25. PACKAGE DRAWINGS.........................................................
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μPD17062 1. PINS 1.1 PIN FUNCTIONS Pin No. Symbol Description Output type At power-on reset DIP QFP (GC) 1 58 P0C3 4-bit output port CMOS push-pull Undefined | | | 4 61 P0C0 5 62 P0D3/ADC5 Input of port 0D and A/D converter — Input | | | • P0D3 to P0D0 8 1 P0D0/ADC2 4-bit input port containing a pull-down resis- tor. • ADC5 to ADC2 Input of a 4-bit A/D converter, which is a soft- ware-based successive-approximation type. The reference voltage is VDD. Output of a 6-bit D/A converter. The out
Summary of the content on the page No. 12
μPD17062 Pin No. Symbol Description Output type At power-on reset DIP QFP (GC) 21 20 P1A3 4-bit output port. This N-ch open-drain output N-ch open-drain Undefined | | | port has an intermediate withstand voltage. 24 24 P1A0 26 27 P1B3 4-bit I/O port. Each bit can be set for input or CMOS push-pull Input | | | output. 29 30 P1B0 30 31 RED Outputs the character data corresponding to R, G, CMOS push-pull Low level 31 32 GREEN and B of the IDC display. The output is active- 32 33 BLUE high. 33 34
Summary of the content on the page No. 13
μPD17062 Pin No. Symbol Description Output type At power-on reset DIP QFP (GC) 48 55 INTNC Interrupt input. Contains the noise canceler. An — Input interrupt can be generated at either the rising or falling edge of the input signal. — 5 NC No connection. The pins are not connected to the 6 internal circuit of the device. They can be used as 7 desired. 8 10 12 14 22 25 37 39 40 41 42 44 56 57 13
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μPD17062 1.2 EQUIVALENT CIRCUITS OF THE PINS P0A (P0A3/SO, P0A2/SCK) P0B (P0B1, P0B0/SI) P1B (P1B3, P1B2, P1B1, P1B0) P1C (P1C3/ADC1, P1C2, P1C1) A/D converter (only for P1C/ADC) VDD RESET signal (except for P1C) Read instruction (only for P1C) VDD P0A (P0A1/SCL, P0A0/SDA) (I/O) 14
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μPD17062 P0C (P0C3, P0C2, P0C1, P0C0) RED, GREEN, BLUE, BLANK, PSC (Output) PWM (PWM3, PWM2, PWM1, PWM0) P1A (P1A3, P1A2, P1A1, P1A0) (Output) P0D (P0D3/ADC5, P0D2/ADC4, P0D1/ADC3, P0D0/ADC2) A/D Converter (Input) High on-state resistance ADC0 A/D converter selection signal 15
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μPD17062 P0B3/HSCNT Port P-ch Horizontal synchronizing signal counter N-ch P0B2/TMIN Port P-ch Timer/counter N-ch 16
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μPD17062 HSYNC, VSYNC, INTNC, CE (Hysteresis input) XOUT, XIN XIN XOUT EO VCO (Input) 17
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μPD17062 2. PROGRAM MEMORY (ROM) Program memory stores the program to be executed by the CPU, as well as predetermined constant data. 2.1 CONFIGURATION OF PROGRAM MEMORY Fig. 2-1 shows the configuration of program memory. As shown in Fig. 2-1, the capacity of the program memory is 8K bytes (3968 × 16 bits). Locations in program memory are addressed in units of 16 bits. The total address range is from 0000H to 0F7FH. Memory is divided into pages. The range of page 0 is from 0000H to 07FFH,
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μPD17062 2.2 FUNCTIONS OF PROGRAM MEMORY Program memory has two basic functions: (1) Program storage (2) Constant data storage A program is a set of instructions that control the CPU (Central Processing Unit: Device that actually controls the microcontroller). The CPU executes processing sequentially according to the instructions coded in the program. The CPU sequentially reads instructions from the program stored in program memory and executes processing according to each instruction. Ea
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μPD17062 2.4 BRANCHING A PROGRAM A program is branched by execution of the branch instruction (BR). Fig. 2-2 illustrates the operation of the branch instruction. Branch instructions (BR) are divided into two types. Direct branch instructions (BR addr) transfer control to a program memory address (addr) directly specified in its operand. Indirect branch instructions (BR @AR) transfer control to a program memory address specified in an address register (AR), described below. See also Chapter 3
