NEC PD75P402 user manual

User manual for the device NEC PD75P402

Device: NEC PD75P402
Category: Computer Hardware
Manufacturer: NEC
Size: 0.9 MB
Added : 4/28/2014
Number of pages: 195
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Abstracts of contents
Summary of the content on the page No. 1

USER'S MANUAL
μPD75402A
4-BIT SINGLE-CHIP MICROCOMPUTER
μPD75402A
μPD75P402
Document No. IEU1270C
(O. D. No. IEU-644D)
Date Published March 1994 P
© NEC Corporation 1989 Printed in Japan

Summary of the content on the page No. 2

MS-DOS is a trademark of Microsoft Corporation. PC/AT, PC DOS are trademarks of IBM Corporation. The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectua

Summary of the content on the page No. 3

Major Revisions in This Version Section Description Amendment: Fig. 5-52 “Data Transmission from Slave Device P.117 to Master Device” P.179 to 181 Change: Appendix B “Development Tools” The mark H shows main revised points.

Summary of the content on the page No. 4

PREFACE USER This manual is intended for user engineers who wish to understand the μPD75402A’s, 75P402’s functions and design an application system using them. OBJECTIVE The objective of this manual is for the user to understand the μPD75402A’s, 75P402’s hardware functions shown below. COMPOSITION This manual is composed roughly of the following contents. • General description • Pin functions • Internal block functions • Interrupt • Other internal peripheral functions • Instruction functions REA

Summary of the content on the page No. 5

Related Documentation Device Related Documents Document Name Document Number User's Manual IEU-644 Instruction Application Table IEM-5504 Application Note IEA-638 75X Series Selection Guide IF-151 Development Tool Related Documents Document Name Document Number IE-75000-R/IE-75001-R User's Manual EEU-846 IE-75000-R-EM User's Manual EEU-673 EP-75402C-R User's Manual EEU-701 EP-75402GB-R User's Manual EEU-702 PG-1500 User's Manual EEU-651 Operation RA75X Assembler Package l EEU-731 Language User's

Summary of the content on the page No. 6

CONTENTS CHAPTER 1. GENERAL............................................................................................................................... 1 1.1 OUTLINE OF FUNCTIONS . .......................................................................................................................... 2 1.2 ORDERING INFORMATION AND QUALITY GRADE.................................................................................. 3 1.3 DIFFERENCES BETWEEN μPD75402A AND μPD75402, 75P402........

Summary of the content on the page No. 7

CHAPTER 4. INTERNAL CPU FUNCTIONS ........................................................................................... 31 4.1 PROGRAM COUNTER (PC) ........................................................................................................................... 31 4.2 PROGRAM MEMORY (ROM) . ..................................................................................................................... 32 4.3 DATA MEMORY (RAM) .............................................

Summary of the content on the page No. 8

6.5 MACHINE CYCLES BEFORE INTERRUPT SERVICING .............................................................................. 135 6.6 INTERRUPT APPLICATIONS ........................................................................................................................ 137 CHAPTER 7. STANDBY FUNCTION ....................................................................................................... 141 7.1 STANDBY MODE SETTING AND OPERATION STATES ..................................

Summary of the content on the page No. 9

CONTENTS OF FIGURES Fig. No Title Page 3-1 Static RAM Address Updating Method ............................................................................................. 25 4-1 Program Counter Configuration ......................................................................................................... 31 4-2 Program Memory Map ........................................................................................................................ 32 4-3 Data Memory Map ...............

Summary of the content on the page No. 10

Fig. No. Title Page 5-32 Example of SBI Serial Bus System Configuration ........................................................................... 93 5-33 SBI Transfer Timing ............................................................................................................................. 95 5-34 Bus Release Signal ............................................................................................................................... 96 5-35 Command Signal ....................

Summary of the content on the page No. 11

CONTENTS OF TABLES Table No. Title Page 1-1 Differences Between μPD75402A and μPD75402, 75P402 ................................................................. 4 2-1 Port Pin List ........................................................................................................................................... 11 2-2 List of Pins Other than Port Pins ........................................................................................................ 12 2-3 Port 0’s, 1’s Dual-Functio

Summary of the content on the page No. 12

CHAPTER 1. GENERAL CHAPTER 1. GENERAL The μPD75402A, 75P402 is a CMOS 4-bit single-chip microcomputer adopting the 75X architecture. With its built- in NEC standard serial bus interface (SBI), it is suitable as a slave microcomputer in a multiprocessor system configuration using the 75X, 78K series as the host microcomputer. The μPD75402A has shortened the conventional μPD75402’s minimum instruction execution time to 0.95 μs. The μPD75P402 is also capable of high-speed processing. It is poss

Summary of the content on the page No. 13

CHAPTER 1. GENERAL 1.1 OUTLINE OF FUNCTIONS Item Description Number of basic 37 instructions Instruction • 0.95 μs, 1.91 μs, 15.3 μs (at 4.19 MHz operation) execution time selectable between 3 levels Built-in Program 1920 × 8 bits (μPD75402A: Mask ROM, μPD75P402: One-time PROM) memory memory Data 64 × 4 bits (RAM) memory General register 4 bits × 4, or 8 bits × 2 (memory mapping) Accumulators 3 accumulators to suit manipulation data length • Bit accumulator (CY), 4-bit accumulator (A), 8-bit a

Summary of the content on the page No. 14

CHAPTER 1. GENERAL 1.2 ORDERING INFORMATION AND QUALITY GRADE (1) Ordering Information Ordering Code Package Program Memory μPD75402AC-××× 28-pin plastic DIP (600 mil) Mask ROM μPD75402ACT-××× 28-pin plastic shrink DIP (400 mil) μPD75402AGB-×××-3B4 44-pin plastic QFP ( n n 10mm) μPD75P402C 28-pin plastic DIP (600 mil) One-time PROM μPD75P402CT 28-pin plastic shrink DIP (400 mil) μPD75P402GB-3B4 44-pin plastic QFP ( n n 10mm) ×××: ROM code number (2) Quality Grade Standard Please refer to “Qual

Summary of the content on the page No. 15

CHAPTER 1. GENERAL 1.3 DIFFERENCES BETWEEN μPD75402A AND μPD75402, 75P402 Table 1-1 shows the differences between the μPD75402A and the μPD75402, 75P402. Otherwise the μPD75402A and the μPD75402, 75P402 have the same functions and are pin-compatible. Table 1-1 Differences Between μPD75402A and μPD75402, 75P402 Item μPD75402A μPD75402 μPD75P402 ROM configuration Mask ROM One-time PROM Instruction 0.95, 1.91, 15.3 μs 1.91, 15.3 μs* 0.95, 1.91, 15.3 μs execution time (at 4.19 MHz operation) (at 4

Summary of the content on the page No. 16

CHAPTER 1. GENERAL 1.4 BLOCK DIAGRAM 5 PORT0 4 P00-P03 BASIC PROGRAM ALU CY SP (5) INTERVAL COUNTER(11) TIMER PORT1 2 P10, P12 INTBT PORT2 4 P20-P23 SI SERIAL ROM (PROM) SO/SB0 INTERFACE 4 PORT3 P30-P33 PROGRAM GENERAL REG. SCK MEMORY DECODE INTCSI AND PORT5 4 P50-P53 CONTROL RAM DATA MEMORY 64 x 4 bits 1920 × 8 bits 4 PORT6 P60-P63 INT0 INTERRUPT CONTROL INT2 N fxx/2 CPU CLOCK CLOCK ø CLOCK CLOCK STAND BY OUTPUT DIVIDER GENER

Summary of the content on the page No. 17

μPD75402AC/CT-××× μPD75P402C/CT-CT CHAPTER 1. GENERAL 1.5 PIN CONFIGURATION 1.5.1 28-Pin Plastic Dip (600 mil), Shrink Dip (400 mil) (1) Normal operating mode * VDD (VPP) NC 1 28 X1 RESET 2 27 X2 P00 3 26 P12/INT2 P01/SCK 4 25 P10/INT0 5 P02/SO/SB0 24 P23 P03/SI 6 23 P22/PCL P50 7 22 P21 P51 8 21 P20 9 P52 20 P63 P53 10 19 P62 11 P30 18 P61 12 P31 17 P60 P32 13 16 P33 14 15 VSS P00 to P03 : Port 0 SCK : Serial clock input/output P10, P12

Summary of the content on the page No. 18

μPD75P402C/CT CHAPTER 1. GENERAL (2) PROM mode 1 VPP 28 VDD 2 A12 27 A14 3 A7 26 A13 4 25 A8 A6 A5 5 24 A9 6 A4 23 A11 7 22 OE A3 8 A10 A2 21 9 20 CE A1 10 A0 19 O7 11 O0 18 O6 12 O1 17 O5 O2 13 16 O4 14 VSS 15 O3 A0 to A14 : Address input O0 to O7 : Data input/output CE : Chip enable input OE : Output enable input VDD : Power supply VPP : Program power supply VSS : Ground 7

Summary of the content on the page No. 19

CHAPTER 1. GENERAL 1.5.2 44-Pin Plastic QFP ( nn 10mm) (1) Normal operating mode 44 43 42 41 40 39 38 37 36 35 34 1 P30 P01/SCK 33 2 P31 P00 32 3 P32 31 RESET NC 4 30 NC (VPP)* VSS 5 NC 29 μPD75402AGB-×××-3B4 NC 6 NC 28 μPD75P402GB-×××-3B4 NC 7 NC 27 8 P33 26 VDD P60 9 25 X1 10 P61 24 X2 NC 11 23 NC 12 13 14 15 16 17 18 19 20 21 22 Remarks Parentheses for the μPD75P402. * If using the μPD75P402 and the printed circuit board com

Summary of the content on the page No. 20

CHAPTER 1. GENERAL (2) PROM mode 44 43 42 41 40 39 38 37 35 34 36 A6 O0 1 33 2 O1 A7 32 O2 3 A12 31 4 30 VPP NC VSS 5 NC 29 6 NC μPD75P402GB-3B4 28 NC 7 NC NC 27 VDD O3 8 26 A14 O4 9 25 O5 10 24 A13 11 23 NC NC 12 13 14 15 16 17 18 19 20 21 22 9 O6 A0 O7 A1 CE A2 A10 NC NC NC VSS NC NC NC OE A3 A11 A4 A9 A5 A8 NC


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