Instrukcja obsługi Sony XR-C6100

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XR-C6100
SERVICE MANUAL Saudi Arabia Model
Dolby noise reduction manufactured under license
Model Name Using Similar Mechanism NEW
from Dolby Laboratories Licensing Corporation.
Tape Transport Mechanism Type MG-25F-136
“DOLBY” and the double-D symbol a are trade-
marks of Dolby Laboratories Licensing Corporation.
SPECIFICATIONS
– Continued on next page –
FM/MW/SW CASSETTE CAR STEREO
MICROFILM

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SECTION 6 DIAGRAMS 6-1. IC PIN FUNCTION DESCRIPTION • MAIN BOARD IC501 m PD78058GC-F58-3B9 (SYSTEM CONTROLLER) Pin No. Pin Name I/O Function Destination setting terminal Frequency select switch (S502) input in this set 1 DSEL I “L”: MW 9k step or FM 50k step, “H”: MW 10k step or FM 200k step 2 RC IN0 I Rotary remote commander shift key A/D input terminal Station detector detect input from the FM/AM tuner unit (TU1) 3 SD IN I Stop level for SEEK, BTM, etc. is determined SD is present

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Pin No. Pin Name I/O Function Loading/tape operation motor control signal output to the LB1638M (IC361) 37 LM EJ O (For the eject direction and reverse side operation) *1 Forward/reverse direction control signal output to the CXA2510AQ (IC301) 38 N/R OUT O “L: forward direction, “H”: reverse direction 39 P.ON O Polar stereo detection signal output terminal “H”: polar stereo Not used (open) 40 CM ON O Capstan/reel motor (M901) drive signal output terminal “H”: motor on 41 TAPEON O Tap

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Pin No. Pin Name I/O Function Input of acknowledge signal for the key entry Acknowledge signal is input to accept function 67 KEYACK I and eject keys in the power off status On at input of “H” 68 VDD — Power supply terminal (+5V) 69 X OUT O Main system clock output terminal (5 MHz) 70 X IN I Main system clock input terminal (5 MHz) 71 GND — Ground terminal 72 XT OUT O Sub system clock output terminal (32.768 kHz) 73 XT IN I Sub system clock input terminal (32.768 kHz) 74 AVDD — Power suppl

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XR-C6100 6-4. SCHEMATIC DIAGRAM – MAIN Section (1/2) – • See page 31 and 32 for IC Block Diagrams. – 23 – – 24 –

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XR-C6100 6-5. SCHEMATIC DIAGRAM – MAIN Section (2/2) – • See page 32 for IC Block Diagramas. • Waveforms 1 IC1 1 (XO) 4.2 Vp-p 7.2 MHz 2 IC501 ^» (XOUT) 4.6 Vp-p 5 MHz 3 IC501 &ª (XT_OUT) 5 Vp-p 32.768 kHz – 25 – – 26 –

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XR-C6100 6-7. SCHEMATIC DIAGRAM – PANEL Section – – 29 – – 30 –

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• IC Block Diagrams – MAIN BOARD – IC1 BU2624F-E2 IC301 CXA2510AQ-T4 XOUT 1 20 VSS REFERENCE 2 30 29 28 27 26 25 24 23 22 21 XIN PHASE DIVIDER 19 PD1 DETECT 120μ/ NR 70μ T2 + – 18 VDD 20 MSMODE – + NR BIAS MS PBFB1 31 19 DRSW X1 MODE I/O PBRIN1 32 CE 3 TAPE/AUX CONTROL 18 TAPESW 17 FMIN 33 F2 PBREF1 17 INSW CK 4 TAPE EQ PBFIN1 34 NR 16 NRSW MODE FWD/RVS DA 5 MAIN 16 AMIN VCT 35 COUNT VCT CD 6 PBGND 36 VCC 15 NC MS ON/ OFF + LPF + DETECT SHIFT – 7 PRESCALLER P0 REGISTER 14 MSOUT PBFIN2 37 LATCH