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PRELIMINARY
CY14B104K, CY14B104M
4 Mbit (512K x 8/256K x 16) nvSRAM with
Real Time Clock
■ Watchdog timer
Features
■ Clock alarm with programmable interrupts
■ 20 ns, 25 ns, and 45 ns access times
■ Capacitor or battery backup for RTC
■ Internally organized as 512K x 8 (CY14B104K) or 256K x 16
(CY14B104M)
■ Commercial and industrial temperatures
■ Hands off automatic STORE on power down with only a small
■ 44 and 54-pin TSOP II package
capacitor
■ Pb-free and RoHS compliance
®
■ STORE to Quant
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PRELIMINARY CY14B104K, CY14B104M Pinouts Figure 1. Pin Diagram - 44-PIn and 54-Pin TSOP II INT 54 HSB 1 INT 1 44 HSB [5] [4] [5] NC 53 NC 2 NC 2 NC 43 [4] A A 0 52 3 17 A 3 42 NC 0 A 51 A 1 4 16 A 4 A 1 41 18 A 50 A 2 5 15 A 5 A 49 2 40 A OE 17 3 6 48 A A BHE 6 39 A 4 7 3 16 47 CE 8 BLE A 7 38 4 A 15 DQ 46 DQ 0 9 15 CE 8 37 OE 54 - TSOP II DQ 10 45 DQ 1 14 DQ 9 44 - TSOP II DQ 0 36 7 DQ 11 44 DQ 2 (x16) 13 (x8) DQ 10 35 DQ 1 DQ 43 DQ 6 12 3 12 V 11 V 42 CC 34 V CC V 13 SS Top View SS Top View
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PRELIMINARY CY14B104K, CY14B104M Table 1. Pin Definitions (continued) Pin Name I/O Type Description Output Interrupt Output. Programmable to respond to the clock alarm, the watchdog timer, and the power INT monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain). V Ground Ground for the Device. Must be connected to ground of the system. SS V Power Supply Power Supply Inputs to the Device. 3.0V +20%, –10% CC Input/Output Hardware STORE Busy (HSB). When LOW this outpu
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PRELIMINARY CY14B104K, CY14B104M power-on-recall, the MPU must be active or the WE held inactive To initiate the Software STORE cycle, the following read until the MPU comes out of reset. sequence must be performed: 1. Read address 0x4E38 Valid READ To reduce unnecessary nonvolatile STOREs, AutoStore and Hardware STORE operations are ignored unless at least one 2. Read address 0xB1C7 Valid READ write operation has taken place since the most recent STORE or 3. Read address 0x83E0 Valid READ RECAL
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PRELIMINARY CY14B104K, CY14B104M Table 2. Mode Selection [3] [6] Mode I/O Power A - A CE WE OE, BHE, BLE 15 0 H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active [7] L H L 0x4E38 Read SRAM Output Data Active 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8B45 AutoStore Output Data Disable [7] L H L 0x4E38 Read SRAM Output Data Active 0xB1C7 Read SRAM Output Dat
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PRELIMINARY CY14B104K, CY14B104M Setting the Clock Data Protection Setting the write bit ‘W’ (in the flags register at 0x7FFF0) to a ‘1’ The CY14B104K/CY14B104M protects data from corruption stops updates to the time keeping registers and enables the time during low voltage conditions by inhibiting all externally initiated to be set. The correct day, date, and time is then written into the STORE and write operations. The low voltage condition is registers and must be in 24 hour BCD format. The t
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PRELIMINARY CY14B104K, CY14B104M must be set to ‘1’. This turns off the oscillator circuit, extending toggle at a nominal frequency of 512 Hz. Any deviation the battery life. If the OSCEN bit goes from disabled to enabled, measured from the 512 Hz indicates the degree and direction of it takes approximately one second (two seconds maximum) for the required correction. For example, a reading of 512.01024 Hz the oscillator to start. indicates a +20 ppm error. Hence, a decimal value of –10 (001010b
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PRELIMINARY CY14B104K, CY14B104M New time out values are written by setting the watchdog write bit determine the cause of the interrupt. The INT pin driver has two to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out bits that specify its behavior when an interrupt occurs. value bits D5-D0 are enabled to modify the time out value. When An Interrupt is raised only if both a flag is raised by one of the WDW is ‘1’, writes to bits D5-D0 are ignored. The WDW function three sources and th
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PRELIMINARY CY14B104K, CY14B104M Figure 4. RTC Recommended Component Configuration Recommended Values Y = 32.768 KHz (6 pF) 1 C = 21 pF 1 C = 21 pF 2 Note: The recommended values for C1 and C2 include board trace capacitance. C1 X 1 Y1 C2 X 2 Figure 5. Interrupt Block Diagram WDF Watchdog WDF - Watchdog Timer Flag Timer WIE WIE - Watchdog Interrupt Enable V P/L CC PF PF - Power Fail Flag Power PFE - Power Fail Enable Pin Monitor INT AF - Alarm Flag PFE Driver AIE - Alarm Interrupt Enable
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PRELIMINARY CY14B104K, CY14B104M [8] Table 4. RTC Register Map [9] Register BCD Format Data Function/Range CY14B104K CY14B104M D7 D6 D5 D4 D3 D2 D1 D0 0x7FFFF 0x3FFFF 10s Years Years Years: 00–99 0x7FFFE 0x3FFFE 0 0 0 10s Months Months: 01–12 Months 0x7FFFD 0x3FFFD 0 0 10s Day of Month Day Of Month Day of Month: 01–31 0x7FFFC 0x3FFFC 0 0 0 0 0 Day of week Day of week: 01–07 0x7FFFB 0x3FFFB 0 0 10s Hours Hours Hours: 00–23 0x7FFFA 0x3FFFA 0 10s Minutes Minutes Minutes: 00–59 0x7FFF9 0x3FFF9 0 10
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PRELIMINARY CY14B104K, CY14B104M Table 5. Register Map Detail Register Description CY14B104K CY14B104M Time Keeping - Years 0x7FFFF 0x3FFFF D7 D6 D5 D4 D3 D2 D1 D0 10s Years Years Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99. Time Keeping - Months 0x7FFFE 0x3FFFE D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 10s Month Month
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PRELIMINARY CY14B104K, CY14B104M Table 5. Register Map Detail (continued) Register Description CY14B104K CY14B104M Calibration/Control 0x7FFF8 0x3FFF8 D7 D6 D5 D4 D3 D2 D1 D0 OSCEN 0 Calibration Calibration Sign OSCEN Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs. Disabling the oscillator saves battery or capacitor power during storage. Calibration Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0
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PRELIMINARY CY14B104K, CY14B104M Table 5. Register Map Detail (continued) Register Description CY14B104K CY14B104M Alarm - Hours 0x7FFF4 0x3FFF4 D7 D6 D5 D4 D3 D2 D1 D0 M 10s Alarm Hours Alarm Hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value. M Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the hours value. Alarm - Minutes 0x7FFF3 0x3FFF3 D7 D6 D5 D4 D3 D2
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PRELIMINARY CY14B104K, CY14B104M Transient Voltage (<20 ns) on Maximum Ratings Any Pin to Ground Potential .................. –2.0V to V + 2.0V CC Exceeding maximum ratings may impair the useful life of the Package Power Dissipation device. These user guidelines are not tested. Capability (T = 25°C) ................................................... 1.0W A Storage Temperature ................................. –65 °C to +150 °C Surface Mount Pb Soldering Temperature (3 Seconds)................
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PRELIMINARY CY14B104K, CY14B104M Data Retention and Endurance Parameter Description Min Unit DATA Data Retention 20 Years R NV Nonvolatile STORE Operations 200 K C Capacitance [14] In the following table, the capacitance parameters are listed. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25 °C, f = 1 MHz, 7pF IN A V = 0 to 3.0V CC C Output Capacitance 7 pF OUT Thermal Resistance [14] In the following table, the thermal resistance parameters are listed. Parameter Desc
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PRELIMINARY CY14B104K, CY14B104M Table 6. RTC Characteristics Parameters Description Test Conditions Min Typ Max Units [15] o I RTC Backup Current Room Temperature (25 C) 300 nA BAK o Hot Temperature (85 C) 450 nA V RTC Battery Pin Voltage 1.8 3.0 3.3 V RTCbat V RTC Capacitor Pin Voltage 1.5 3.0 3.6 V RTCcap tOCS RTC Oscillator Time to Start 1 2 sec Notes 15. From either V or V RTCcap RTCbat. Document #: 001-07103 Rev. *K Page 16 of 31 [+] Feedback
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PRELIMINARY CY14B104K, CY14B104M AC Switching Characteristics Parameters 20 ns 25 ns 45 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameters Parameters SRAM Read Cycle t t Chip Enable Access Time 20 25 45 ns ACE ACS [16] t t Read Cycle Time 20 25 45 ns RC RC [17] t t Address Access Time 20 25 45 ns AA AA t t Output Enable to Data Valid 10 12 20 ns DOE OE [17] t t Output Hold After Address Change 3 3 3 ns OHA OH [14, 18] t t Chip Enable to Output Active 3 3 3 ns LZCE LZ [14, 18] t
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PRELIMINARY CY14B104K, CY14B104M Switching Waveforms [3, 16, 20] Figure 8. SRAM Read Cycle 2: CE Controlled Address Address Valid t t RC HZCE t ACE CE t AA t t LZCE HZOE t DOE OE t t LZOE HZBE t DBE BHE, BLE t LZBE High Impedance Data Output Output Data Valid t PU t PD Active I Standby CC [3, 19, 20, 21] Figure 9. SRAM Write Cycle 1: WE Controlled t WC Address Address Valid t t SCE HA CE t BW BHE, BLE t AW t PWE WE t SA t t HD SD Data Input Input Data Valid t t LZWE HZWE High Impedance Data O
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PRELIMINARY CY14B104K, CY14B104M Switching Waveforms [3, 19, 20, 21] Figure 10. SRAM Write Cycle 2: CE Controlled t WC Address Valid Address t t t SA SCE HA CE t BW BHE, BLE t PWE WE t t SD HD Data Input Input Data Valid High Impedance Data Output [6, 19, 20, 21, 22] Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled (Not applicable for RTC register writes) t WC Address Address Valid t SCE CE t t t SA HA BW BHE, BLE t AW t PWE WE t t SD HD Data Input Input Data Valid High Impedance Data Ou
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PRELIMINARY CY14B104K, CY14B104M AutoStore/Power Up RECALL 20 ns 25 ns 45 ns Parameters Description Unit Min Max Min Max Min Max [23] t Power Up RECALL Duration 20 20 20 ms HRECALL [24] t STORE Cycle Duration 8 8 8 ms STORE [25] t Time Allowed to Complete SRAM Cycle 20 25 25 ns DELAY V Low Voltage Trigger Level 2.65 2.65 2.65 V SWITCH t VCC Rise Time 150 150 150 μs VCCRISE [14] V HSB Output Driver Disable Voltage 1.9 1.9 1.9 V HDIS t HSB To Output Active Time 5 5 5 μs LZHSB t HSB High Active
