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Mobile 3rd Generation Intel
Core™ Processor Family
Specification Update
September 2013
Revision 015
Reference Number: 326770
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Contents Contents Revision History...............................................................................................................5 Preface ..............................................................................................................................6 Summary Tables of Changes..........................................................................................8 Identification Information .......................................................................
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Contents 4 Specification Update
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Revision History Revision Description Date 001 • Initial Release. April 2012 • Added Errata BU69–BU85 002 May 2012 • Updated Processor Identification Table • Added L-1 stepping to Component Identification using Programming 003 • Added L-1 stepping to errata summary table June 2012 • Updated Processor Identification Table 004 • Added Errata BU86-BU90 June 2012 ® • Added Mobile 3rd Generation Intel Core™ i7-3940XM, i7-3840QM, i7-3740QM 005 October 2012 processors 006 • Added Errata BU91-BU94 No
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Preface This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also co
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Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics such as, core speed, L2 cache size, package type, etc. as described in the processor iden
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Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations: Codes Used in Summary Tables Stepping X: Errata exists in the stepping indicated. Specification Change
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Errata (Sheet 2 of 5) Steppings Number Status ERRATA E-1 L-1 General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be BU7 XX No Fix Preempted LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in BU8 XX No Fix 64-bit Mode Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR or XSAVE/XRSTOR BU9 XX No Fix Image Leads to Partial Memory Update BU10 XX No Fix Values for LBR/BTS/BTM Will be Incorrect after an Exit from SMM EFLAGS Discrepancy on
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Errata (Sheet 3 of 5) Steppings Number Status ERRATA E-1 L-1 BU34 XX No Fix Processor May Fail to Acknowledge a TLP Request BU35 XX No Fix An Unexpected PMI May Occur After Writing a Large Value to IA32_FIXED_CTR2 A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain BU36 XX No Fix Conditions BU37 XX No Fix PCIe* LTR Incorrectly Reported as Being Supported BU38 XX No Fix PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have Occurred #GP May be Signaled
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Errata (Sheet 4 of 5) Steppings Number Status ERRATA E-1 L-1 PCIe* Root-port Initiated Compliance State Transmitter Equalization Settings May be BU63 XX No Fix Incorrect BU64 XX No Fix PCIe* Controller May Incorrectly Log Errors on Transition to RxL0s Reception of Certain Malformed Transactions May Cause PCIe* Port to Hang Rather BU65 XX No Fix Than Reporting an Error BU66 XX No Fix PCIe* Link Width May Degrade After a Warm Reset BU67 XX No Fix MSR_PKG_Cx_RESIDENCY MSRs May Not be Accurate
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Errata (Sheet 5 of 5) Steppings Number Status ERRATA E-1 L-1 Instruction Fetches Page-Table Walks May be Made Speculatively to Uncacheable BU94 X X No Fix Memory BU95 X X No Fix The Processor May Not Properly Execute Code Modified Using A Floating-Point Store BU96 X X No Fix Execution of GETSEC[SEXIT] May Cause a Debug Exception to be Lost VM Exits Due to GETSEC May Save an Incorrect Value for “Blocking by STI” in the BU97 X X No Fix Context of Probe-Mode Redirection Specific Graphics Blitter
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§ § Specification Update 13
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Identification Information Component Identification using Programming Interface The processor stepping can be identified by the following register contents: Extended Extended Processor Family Model Stepping Reserved 1 2 Reserved 3 4 5 6 Family Model Type Code Number ID 31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0 00000000b 0011b 00b 0110 1010b xxxxb Notes: 1. The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8], to indicate whether the processo
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Component Marking Information The processor stepping can be identified by the following component markings. Table 1. Processor Identification (Sheet 1 of 6) Core Frequency ® Max Intel (GHz) / Turbo Boost Shared Processor Processor DDR3 (MHz) / Number Stepping Technology L3 Cache Notes Number Signature Processor 2.0 Frequency Size (MB) Graphics 1 (GHz) Frequency 3/4 core: 3.6 SR0T2 i7-3920XM E-1 000306A9h 2.9 / 1600 / 650 2 core: 3.7 8 2,3,4,5,6 1 core: 3.8 3/4 core: 3.5 SR0MJ i7-3820QM
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Table 1. Processor Identification (Sheet 2 of 6) Core Frequency ® Max Intel (GHz) / Turbo Boost Shared Processor Processor DDR3 (MHz) / Number Stepping Technology L3 Cache Notes Number Signature Processor 2.0 Frequency Size (MB) Graphics 1 (GHz) Frequency 4 core: 0 3 core: 0 SR0MX i5-3320M L-1 000306A9h 2.6 / 1600 / 650 3 2,3,4,5,6 2 core: 3.1 1 core: 3.3 4 core: 0 3 core: 0 SR0MY i5-3320M L-1 000306A9h 2.6 / 1600 / 650 3 2,3,4,5,6 2 core: 3.1 1 core: 3.3 4 core: 0 3 core: 0 SR0MZ i5-3210
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Table 1. Processor Identification (Sheet 3 of 6) Core Frequency ® Max Intel (GHz) / Turbo Boost Shared Processor Processor DDR3 (MHz) / Number Stepping Technology L3 Cache Notes Number Signature Processor 2.0 Frequency Size (MB) Graphics 1 (GHz) Frequency 2 core: 3.4 SR0X7 i5-3380M L-1 000306A9h 2.9 /1600 /650 3 2,3,4,5,6 1 core: 3.6 2 core: 3.4 SR0X9 i5-3380M L-1 000306A9h 2.9 /1600 /650 3 2,3,4,5,6 1 core: 3.6 2 core: 3.2 SR0XA i5-3340M L-1 000306A9h 2.7 / 1600 /650 3 2,3,4,5,6 1 core
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Table 1. Processor Identification (Sheet 4 of 6) Core Frequency ® Max Intel (GHz) / Turbo Boost Shared Processor Processor DDR3 (MHz) / Number Stepping Technology L3 Cache Notes Number Signature Processor 2.0 Frequency Size (MB) Graphics 1 (GHz) Frequency 2 core: N/A SR0ZN i5-3439Y L-1 000306A9h 1.5 /1600/ 350 3 2,3,4,5,6 1 core: 2.3 2 core: N/A SR12S i5-3339Y L-1 000306A9h 1.5 /1600/ 350 3 2,4,5,6 1 core: 2.2 2 core: N/A SR0ZQ i5-3339Y L-1 000306A9h 1.5 /1600/ 350 3 2,4,5,6 1 core: 2.2 2
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Table 1. Processor Identification (Sheet 5 of 6) Core Frequency ® Max Intel (GHz) / Turbo Boost Shared Processor Processor DDR3 (MHz) / Number Stepping Technology L3 Cache Notes Number Signature Processor 2.0 Frequency Size (MB) Graphics 1 (GHz) Frequency 3/4 Core: 2.8 SR0ND i7-3612QE E-1 00306A9h 2.3 / 1600/ 650 2 Core: 3.0 6 2,3,4,5,6,8 1 Core: 3.1 4 Core: 0 3 Core: 0 SR0T5 i7-3555LE L-1 00306A9h 2.5 / 1600/ 550 4 2,3,4,5,6,8 2 Core: 3.0 1 Core: 3.2 4 Core: 0 3 Core: 0 SR0T6 i7-3517UE
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Table 1. Processor Identification (Sheet 6 of 6) Core Frequency ® Max Intel (GHz) / Turbo Boost Shared Processor Processor DDR3 (MHz) / Number Stepping Technology L3 Cache Notes Number Signature Processor 2.0 Frequency Size (MB) Graphics 1 (GHz) Frequency 4 Core: 0 3 Core: 0 SR0VR 1020E P-0 00306A9h 2.2 / 1600/ 650 24,8 2 Core: 0 1 Core: 0 4 Core: 0 3 Core: 0 SR10F 927UE P-0 00306A9h 1.5 / 1600/ 350 14,8 2 Core: 0 1 Core: 0 Notes: ® 1. This column indicates maximum Intel Turbo Boost Techn
