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Spartan-3A DSP FPGA Family:
Data Sheet
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DS610 July 16, 2007 Product Specification
Module 1:
Introduction and Ordering Information
� UG332: Spartan-3 Generation Configuration User Guide
- Configuration Overview
DS610-1 (v2.0) July 16, 2007
- Configuration Pins and Behavior
• Introduction
- Bitstream Sizes
� Features
- Detailed Descriptions by Mode
� Architectural Overview
· Master Serial Mode using Platform Flash PROM
� Configuration Overview
· Master SPI Mode using Commodity Serial
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R Data Sheet 2 www.xilinx.com DS610 July 16, 2007 Product Specification This page intentionally left blank.
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< B R Spartan-3A DSP FPGA Family: L Introduction and Ordering Information B DS610-1 (v2.0) July 16, 2007 Product Specification ♦ Available pipeline stages for enhanced performance of at least Introduction 250 MHz in the standard -4 speed grade ♦ 48-bit accumulator for multiply-accumulate (MAC) operation The Spartan™-3A DSP family of Field-Programmable Gate Arrays ♦ Integration added for complex multiply or multiply-add operation (FPGAs) solves the design challenges in most high-volume, ♦ In
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R Introduction and Ordering Information Architectural Overview The Spartan-3A DSP family architecture consists of five After applying power, the configuration data is written to the fundamental programmable functional elements: FPGA using any of seven different modes: • XtremeDSP DSP48A Slice provides an 18-bit x 18-bit • Master Serial from a Xilinx Platform Flash PROM multiplier, 18-bit pre-adder, 48-bit • Serial Peripheral Interface (SPI) from an post-adder/accumulator, and cascade capabil
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R Introduction and Ordering Information IOBs CLB DCM IOBs DCM CLBs DCM IOBs DS610-1_01_031207 Notes: 1. The XC3SD1800A and XC3SD3400A have two DCMs on both the left and right sides, as well as the two DCMs at the top and bottom of the devices. The two DCMs on the left and right of the chips are in the middle of the outer Block RAM/DSP48A columns of the 4 or 5 columns in the selected device, as shown in the diagram above. 2. A detailed diagram of the DSP48A can be found in UG431: XtremeDSP DSP
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R Introduction and Ordering Information Package Marking Figure 2 shows the top marking for Spartan-3A DSP The “5C” and “4I” Speed Grade/Temperature Range part FPGAs. Use the seven digits of the Lot Code to access combinations may be dual marked as “5C/4I”. additional information for a specific device using the Xilinx web-based Genealogy Viewer. Mask Revision R BGA Ball A1 R SPARTAN Fabrication/ Process Code Device Type XC3SD1800A Date Code Package CSG484XGQ#### X#######X Lot Code Low-Power L4
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R Introduction and Ordering Information Revision History The following table shows the revision history for this document. Date Version Revision 04/02/07 1.0 Initial Xilinx release. 05/25/07 1.0.1 Minor edits. 06/18/07 1.2 Updated for Production release. 07/16/07 2.0 Added Low-power options. DS610-1 (v2.0) July 16, 2007 www.xilinx.com 7 Product Specification
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Functional Description 0 DS610-2 (v2.0) July 16, 2007 Product Specification Introduction The functionality of the Spartan™-3A DSP FPGA family is • UG332: Spartan-3 Generation Configuration User described in the following documents. The topics covered in Guide each guide are listed below. ♦ Configuration Overview • UG431: XtremeDSP DSP48A for Spartan-3A DSP - Configuration Pins and Behavior FPGAs User Guide - Bitstream Sizes ♦ XtremeDSP DSP48A Slices
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R Functional Description 10 www.xilinx.com DS610-2 (v2.0) July 16, 2007 Product Specification This page intentionally left blank.
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DC and Switching Characteristics 0 DS610-3 (v2.0) July 16, 2007 Product Specification DC Electrical Characteristics In this section, specifications may be designated as All parameter limits are representative of worst-case supply Advance, Preliminary, or Production. These terms are voltage and junction temperature conditions. Unless defined as follows: otherwise noted, the published parameter values apply to all Spartan™-3A DSP devices. AC and DC A
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R DC and Switching Characteristics Power Supply Specifications Table 4: Supply Voltage Thresholds for Power-On Reset Symbol Description Min Max Units V Threshold for the V supply 0.4 1.0 V CCINTT CCINT V Threshold for the V supply 0.8 2.0 V CCAUXT CCAUX V Threshold for the V Bank 2 supply 0.8 2.0 V CCO2T CCO Notes: 1. V , V , and V supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash, CCINT CCAUX CCO SPI Flash, parallel NOR Flash, micro
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R DC and Switching Characteristics General DC Characteristics for I/O Pins Table 8: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins Symbol Description Test Conditions Min Typ Max Units I Leakage current at User I/O, Driver is in a high-impedance state, –10 -+10 μA L Input-only, Dual-Purpose, and V = 0V or V max, sample-tested IN CCO Dedicated pins, FPGA powered Leakage current on pins during All pins except INIT_B, PROG_B, DONE, and JTAG pins –10 -+10 μA I HS when PU
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R DC and Switching Characteristics Quiescent Current Requirements Table 9: Quiescent Supply Current Characteristics Commercial Industrial (2) (2) (2) Symbol Description Device Power Typical Maximum Maximum Units I Quiescent V supply current XC3SD1800A C,I 55 390 500 mA CCINTQ CCINT LI 45 - 175 mA XC3SD3400A C,I 80 550 725 mA LI 70 - 300 mA I Quiescent V supply current XC3SD1800A C,I 0.4 4 5 mA CCOQ CCO LI 0.2 -5 mA XC3SD3400A C,I 0.4 4 5 mA -5 mA LI 0.2 I Quiescent V supply current XC3SD1800A
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R DC and Switching Characteristics Single-Ended I/O Standards Table 10: Recommended Operating Conditions for User I/Os Using Single-Ended Standards (2) V for Drivers V V V CCO REF IL IH IOSTANDARD Attribute Min (V) Nom (V) Max (V) Min (V) Nom (V) Max (V) Max (V) Min (V) LVTTL 3.0 3.3 3.6 0.8 2.0 (4) LVCMOS33 3.0 3.3 3.6 0.8 2.0 (4,5) LVCMOS25 2.3 2.5 2.7 0.7 1.7 (4) LVCMOS18 1.65 1.8 1.95 0.38 0.8 V is not used for (4) REF LVCMOS15 1.4 1.5 1.6 0.38 0.8 these I/O standards (4) LVCMOS12 1.1 1.
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R DC and Switching Characteristics Table 11: DC Characteristics of User I/Os Using Table 11: DC Characteristics of User I/Os Using Single-Ended Standards (Continued) Single-Ended Standards Test Logic Level Test Logic Level Conditions Characteristics Conditions Characteristics I I V V I I V V IOSTANDARD OL OH OL OH OL OH OL OH IOSTANDARD Attribute (mA) (mA) Max (V) Min (V) Attribute (mA) (mA) Max (V) Min (V) (5) (3) PCI33_3 1.5 –0.5 10% V 90% V LVTTL 22 –2 0.4 2.4 CCO CCO (5) PCI66_3 1.
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R DC and Switching Characteristics Differential I/O Standards V INP Differential P I/O Pair Pins N Internal V INN Logic V INN V 50% ID V INP V ICM GND level V + V INP INN V = Input common mode voltage = ICM 2 V V - V = Differential input voltage = ID INP INN DS610-3_03_061507 Figure 3: Differential Input Voltages Table 12: Recommended Operating Conditions for User I/Os Using Differential Signal Standards (1) (2) V for Drivers V V CCO ID ICM IOSTANDARD Attribute Min (V) Nom (V) Max (V
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R DC and Switching Characteristics V OUTP Differential P I/O Pair Pins N Internal V OUTN Logic V OH V OUTN V 50% OD V OUTP V OL V OCM GND level V + V OUTP OUTN V = Output common mode voltage = OCM 2 V - V V = Output differential voltage = OUTP OUTN OD V = Output voltage indicating a High logic level OH = Output voltage indicating a Low logic level V OL DS312-3_03_102406 Figure 4: Differential Output Voltages Table 13: DC Characteristics of User I/Os Using Differential Signal Standards
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Bank 1 Bank 1 Bank 1 Bank 1 R DC and Switching Characteristics External Termination Requirements for Differential I/O LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards Bank 0 and 2 Any Bank Bank 0 Bank 0 No VCCO Restrictions 1 / th of Bourns 4 LVDS_33, LVDS_25, Part Number Bank 2 Bank 2 MINI_LVDS_33, Z0 = 50Ω CAT16-PT4F4 MINI_LVDS_25, RSDS_33, RSDS_25, VCCO = 3.3V VCCO = 2.5V PPDS_33, PPDS_25 LVDS_33, LVDS_25, 100Ω MINI_LVDS_33, MINI_LVDS_25, Z0 = 50Ω RSDS_33, RSDS_25, PPDS_33 PPDS_25 DIFF_T
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R DC and Switching Characteristics Switching Characteristics All Spartan-3A DSP FPGAs ship in two speed grades: –4 Software Version Requirements and the higher performance –5. Switching characteristics in Production-quality systems must use FPGA designs this document are designated as Preview, Advance, compiled using a speed file designated as PRODUCTION Preliminary, or Production, as shown in Table 15. Each status. FPGAs designs using a less mature speed file category is defined as follo
