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STK14CA8
128Kx8 AutoStore™ nvSRAM
Features Description
■ 25, 35, 45 ns Read Access and Read/Write Cycle Time The Cypress STK14CA8 is a 1 Mb fast static RAM with a nonvol-
atile QuantumTrap™ storage element included with each
■ Unlimited Read/Write Endurance
memory cell. This SRAM provides fast access and cycle times,
ease of use, and unlimited read and write endurance of a normal
■ Automatic Nonvolatile STORE on Power Loss
SRAM.
■ Nonvolatile STORE Under Hardware or Software Control
Data transfe
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STK14CA8 Pinouts Figure 1. 48-Pin SSOP Figure 2. 32-Pin SOIC V CAP VCAP 1 32 V 1 V CC 48 CC A A 2 47 A 16 2 31 A 16 15 15 A 14 3 46 3 30 HSB A HSB 14 A 12 4 45 W A 12 4 29 W A 7 44 A 5 13 A 28 A 7 5 13 A A 6 6 43 8 A A 6 27 8 6 A 5 42 A 7 9 A 26 5 7 A 9 NC NC 8 41 A 4 25 A 8 11 A 4 40 A 9 11 A 24 3 9 G NC 10 39 NC A 2 23 10 A NC 38 10 11 NC NC A 11 22 12 37 1 E NC V SS 36 A 21 DQ 13 V 0 12 7 SS NC 14 35 NC DQ 20 DQ 0 13 6 NC 34 15 NC DQ DQ 1 14 19 5 DQ DQ 0 16 33 6 DQ 2 18 DQ
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STK14CA8 NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS Absolute Maximum Ratings θ 5.4 C/W; θ 44.3 [0fpm], 37.9 [200fpm], 35.1 C/W [500fpm]. jc ja Voltage on Input Relative to Ground.................–0.5V to 4.1V RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS Voltage on Input Relative to V ...........–0.5V to (V + 0.5V) SS CC θ 6.2 C/W; θ 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm]. jc ja Voltage on DQ or HSB ......................–0.5V to (V + 0.5V) 0-7 CC Temperature under Bias .................
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STK14CA8 AC Test Conditions Input Pulse Levels ....................................................0V to 3V Input Rise and Fall Times ................................................. ≤ 5 ns Input and Output Timing Reference Levels .................... 1.5V Output Load..................................See Figure 4 and Figure 5 Capacitance (T = 25°C, f = 1.0 MHz) A [2] Symbol Parameter Max Units Conditions C Input Capacitance 7 pF ΔV = 0 to 3V IN C Output Capacitance 7 pF ΔV = 0 to 3V OUT Figure
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STK14CA8 SRAM READ Cycles #1 and #2 Symbols STK14CA8-25 STK14CA8-35 STK14CA8-45 NO. Parameter Units #1 #2 Alt. Min Max Min Max Min Max t t Chip Enable Access Time 25 35 45 ns 1 ELQV ACS [3] [3] t t t Read Cycle Time 25 35 45 ns 2 AVAV ELEH RC [4] [4] t t t Address Access Time 25 35 45 ns 3 AVQV AVQV AA t t Output Enable to Data Valid 12 15 20 ns 4 GLQV OE [4] [4] t t t Output Hold after Address Change 3 3 3 ns 5 AXQX AXQX OH t t Address Change or Chip Enable to 33 3 ns 6 ELQX LZ Output Active [5
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STK14CA8 SRAM WRITE Cycles #1 and #2 Symbols STK14CA8-25 STK14CA8-35 STK14CA8-45 NO. Parameter Units #1 #2 Alt. Min Max Min Max Min Max t t t Write Cycle Time 25 35 45 ns 12 AVAV AVAV WC t t t Write Pulse Width 20 25 30 ns 13 WLWH WLEH WP t t t Chip Enable to End of Write 20 25 30 ns 14 ELWH ELEH CW t t t Data Setup to End of Write 10 12 15 ns 15 DVWH DVEH DW t t t Data Hold after End of Write 0 0 0 ns 16 WHDX EHDX DH t t t Address Setup to End of Write 20 25 30 ns 17 AVWH AVEH AW t t t Address
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STK14CA8 AutoStore/POWER UP RECALL Symbols STK14CA8 NO. Parameter Units Notes Standard Alternate Min Max t Power up RECALL Duration 20 ms 9 22 HRECALL t t STORE Cycle Duration 12.5 ms 10, 11 23 STORE HLHZ V Low Voltage Trigger Level 2.65 V 24 SWITCH V V Rise Time 150 μs 25 CCRISE CC t Figure 10. AutoStore/POWER UP RECALL 25 23 23 22 22 Note Read and Write cycles are ignored during STORE, RECALL, and while V is below V CC SWITCH. Notes 9. t starts from the time V rises above V HRECALL CC SWITCH
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STK14CA8 Software Controlled STORE/RECALL Cycle Symbols STK14CA8-35 STK14CA8-35 STK14CA8-45 [12,13] NO. Parameter Units Notes E Cont G Cont Alt Min Max Min Max Min Max t t t STORE/RECALL Initiation Cycle 25 35 45 ns 13 26 AVAV AVAV RC Time t t t Address Setup Time 0 0 0 ns 27 AVEL AVGL AS t t t Clock Pulse Width 20 25 30 ns 28 ELEH GLGH CW t t Address Hold Time 1 1 1 ns 29 EHAX GHAX t t RECALL Duration 50 50 50 μs 30 RECALL RECALL [13] Figure 11. Software STORE/RECALL CYCLE: E Controlled 26 26
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STK14CA8 Hardware STORE Cycle Symbols STK14CA8 NO. Parameter Units Notes Standard Alternate Min Max t t Hardware STORE to SRAM Disabled 1 70 μs 14 31 DELAY HLQZ t Hardware STORE Pulse Width 15 ns 32 HLHX Figure 13. Hardware STORE Cycle 32 23 31 Soft Sequence Commands Symbols Parameter STK14CA8 Units Notes NO. Standard Min Max t Soft Sequence Processing Time 70 μs15, 16 33 SS Figure 14. Software Sequence Commands 33 33 Notes 14. On a hardware STORE initiation, SRAM operation continues to be ena
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STK14CA8 Mode Selection E W G A -A Mode I/O Power Notes 16 0 H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x04E38 Read SRAM Output Data Active 0x0B1C7 Read SRAM Output Data 0x083E0 Read SRAM Output Data 17, 18, 19 0x07C1F Read SRAM Output Data 0x0703F Read SRAM Output Data 0x08B45 AutoStore Disable Output Data L H L 0x04E38 Read SRAM Output Data Active 0x0B1C7 Read SRAM Output Data 0x083E0 Read SRAM Output Data 17, 18,
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STK14CA8 on page 3 for the size of the capacitor. The voltage on the V nvSRAM Operation CAP pin is driven to 5V by a charge pump internal to the chip. A pull up should be placed on W to hold it inactive during power up. nvSRAM To reduce unneeded nonvolatile stores, AutoStore and The STK14CA8 nvSRAM has two functional components paired Hardware Store operations are ignored unless at least one in the same physical cell. These are the SRAM memory cell and WRITE operation has taken place since the m
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STK14CA8 Software STORE Data Protection Data can be transferred from the SRAM to the nonvolatile The STK14CA8 protects data from corruption during low voltage memory by a software address sequence. The STK14CA8 conditions by inhibiting all externally initiated STORE and software STORE cycle is initiated by executing sequential E WRITE operations. The low voltage condition is detected when controlled or G controlled READ cycles from six specific address V
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STK14CA8 Low Average Active Power Preventing AutoStore CMOS technology provides the STK14CA8 with the benefit of The AutoStore function can be disabled by initiating an power supply current that scales with cycle time. Less current is AutoStore Disable sequence. A sequence of READ operations drawn as the memory cycle time becomes longer than 50 ns. is performed in a manner similar to the software STORE initi- Figure 16 shows the relationship between I and CC ation. To initiate the AutoStore Disa
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STK14CA8 Ordering Information STK14CA8-R F 45 ITR Packing Option Blank=Tube TR=Tape and Reel Temperature Range Blank=Commercial (0 to +70 C) I= Industrial (-45 to +85 C) Access Time 25=25 ns 35=35 ns 45=45 ns Lead Finish F=100% Sn (Matte Tin) RoHS Compliant Package N=Plastic 32-pin 300 mil SOIC (50 mil pitch) R=Plastic 48-pin 300 mil SSOP (25 mil pitch) Ordering Codes Part Number Description Access Times Temperature STK14CA8-NF25 3V 128Kx8 AutoStore nvSRAM SOP32-300 25 ns Commercial STK14CA8-NF3
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STK14CA8 Package Diagrams Figure 17. 32-Pin 300 mil SOIC (51-85127) 51-85127 *A Figure 18. 48-Pin 300 mil SSOP (51-85061) 51-85061 *C Document Number: 001-51592 Rev. ** Page 15 of 16 [+] Feedback
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STK14CA8 Document History Page Document Title: STK14CA8 128Kx8 AutoStore™ nvSRAM Document Number: 001-51592 Orig. of Submission Revision ECN Description of Change Change Date ** 2665610 GVCH/PYRS 02/04/09 New data sheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Solut
