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EM78P156N
OTP ROM
EM78P156N
8-BIT MICRO-CONTROLLER
Version 1.2
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EM78P156N OTP ROM Specification Revision History Version Content 1.0 Initial version 1.1 Change Power on reset content 07/01/2003 1.2 Add the Device Characteristic at section 6.3 07/29/2004 Application Note AN-001 EM78P156N v.s. EM78P156E on the DC Characteristics This specification is subject to change without prior notice. 2 07.29.2004 (V1.2)
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EM78P156N OTP ROM 1. GENERAL DESCRIPTION EM78P156N is an 8-bit microprocessor designed and developed with low-power, high-speed CMOS technology.. It is equipped with 1K*13-bits Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides three PROTECTION bits to prevent user’s code in the OTP memory from being intruded. 8 OPTION bits are also available to meet user’s requirements. With its OTP-ROM feature, the EM78P156N is able to offer a convenient way of developing and
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EM78P156N OTP ROM 2. FEATURES • Operating voltage range : 2.5V~5.5V • Operating temperature range: -40 °C~85 °C • Operating frequency rang (base on 2 clocks ): * Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.5V. * ERC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.5V. • Low power consumption: * Less then 2 mA at 5V/4MHz * Typically 20 µA at 3V/32KHz * Typically 1 µA during sleep mode • 1K × 13 bits on chip ROM • One security register to prevent intrusion of OTP
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EM78P156N OTP ROM * 20 pin SSOP 209mil : EM78P156NKM • 99.9% single instruction cycle commands • The transient point of system frequency between HXT and LXT is around 400KHz This specification is subject to change without prior notice. 5 07.29.2004 (V1.2)
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EM78P156NKM EM78P156NAS EM78P156NP EM78P156NM EM78P156N OTP ROM 3. PIN ASSIGNMENTS NC 1 20 NC P52 1 20 P51 P52 1 18 P51 P52 2 19 P51 19 2 P50 P53 2 17 P50 P53 3 18 P50 P53 TCC 3 18 OSCI TCC 3 OSCI 16 TCC 4 17 OSCI 4 17 /RESET OSCO /RESET 4 15 OSCO /RESET 5 16 OSCO Vss 5 16 VDD Vss 5 14 VDD Vss 6 15 VDD Vss 6 15 VDD P60/INT 6 13 P67 P60/INT 7 14 P67 P60/INT 7 14 P67 P61 7 12 P66 P61 8 13 P66 P61 8 13 P66 P62 8 11 P65 P62 9 12 P62 P65 9 12 P65 P63 9 P64 10 P63 10 11 P64 P63 10 11 P64 Fi
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EM78P156N OTP ROM Table 2 EM78P156NAS Pin Description Symbol Pin No. Type Function VDD 15 - * Power supply. * XTAL type: Crystal input terminal or external clock input pin. OSCI 17 I * ERC type: RC oscillator input pin. * XTAL type: Output terminal for crystal oscillator or external clock input pin. OSCO 16 I/O * RC type: Instruction clock output. * External clock signal input. * The real time clock/counter (with Schmitt trigger input pin), must be tied to TCC 4 I VDD or VSS if
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EM78P156N OTP ROM 4. FUNCTION DESCRIPTION OSCO /RESET OSCI TCC /INT WDT timer Oscillator/Timing Control ROM R2 Stack Prescaler IOCA ALU Interrupt Instruction RAM Controller Register R3 R1(TCC) R4 Instruction ACC Decoder DATA & CONTROL BUS P60//INT P61 P62 IOC6 IOC5 P50 I/O I/O P63 P51 PORT 6 P64 PORT 5 P52 R6 R5 P65 P53 P66 P67 Fig. 2 Function Block Diagram 4.1 Operational Registers 1. R0 (Indirect Addressing Register) R0 is not a physically implemented register. Its major function i
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User Memory Space EM78P156N OTP ROM 3. R2 (Program Counter) & Stack • Depending on the device type, R2 and hardware stack are 10-bits wide. The structure is depicted in Fig.3. • Generating 1024 ×13 bits on-chip OTP ROM addresses to the relative programming instruction codes. One program page is 1024 words long. • R2 is set as all "0"s when under RESET condition. • "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to go to any locatio
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EM78P156N OTP ROM Address R PAGE registers IOC PAGE registers 00 R0 (IAR) Reserve 01 R1 (TCC) CONT (Control Register) 02 R2 (PC) Reserve 03 (Status) Reserve R3 04 R4 (RSR) Reserve 05 R5 (Port5) IOC5 (I/O Port Control Register) 06 R6 (Port6) IOC6 (I/O Port Control Register) 07 Reserve Reserve 08 Reserve Reserve 09 Reserve Reserve 0A Reserve IOCA (Prescaler Control Register) 0B Reserve IOCB (Pull-down Register) 0C Reserve IOCC (Open-drain Control) 0D Reserve (Pull-high Control
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EM78P156N OTP ROM 4. R3 (Status Register) 7 6 5 4 3 2 1 0 GP2 GP1 GP0 T P Z DC C • Bit 0 (C) Carry flag • Bit 1 (DC) Auxiliary carry flag • Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. • Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. • Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and "WDTC" commands, or during power up and reset to 0 by WDT time-out. • Bit5 ~7 (GP0 ~
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EM78P156N OTP ROM • RF can be cleared by instruction but cannot be set. • IOCF is the interrupt mask register. • Note that the result of reading RF is the "logic AND" of RF and IOCF. 8. R10 ~ R3F • All of these are 8-bit general-purpose registers. 4.2 Special Purpose Registers 1. A (Accumulator) • Internal data transfer, or instruction operand holding • It cannot be addressed. 2. CONT (Control Register) 7 6 5 4 3 2 1 0 - /INT TS TE PAB PSR2 PSR1 PSR0 • Bit 0 (PSR0) ~ Bit 2 (PSR
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EM78P156N OTP ROM • CONT register is both readable and writable. 3. IOC5 ~ IOC6 (I/O Port Control Register) • "1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output. • Only the lower 4 bits of IOC5 can be defined. • IOC5 and IOC6 registers are both readable and writable. 4. IOCA (Prescaler Counter Register) • IOCA register is readable. • The value of IOCA is equal to the contents of Prescaler counter. • Down counter. 5. IOCB (Pull-down C
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EM78P156N OTP ROM • Bit 5 (OD5) Control bit is used to enable the open-drain of P65 pin. • Bit 6 (OD6) Control bit is used to enable the open-drain of P66 pin. • Bit 7 (OD7) Control bit is used to enable the open-drain of P67 pin. • IOCC Register is both readable and writable. 7. IOCD (Pull-high Control Register) 7 6 5 4 3 2 1 0 /PH7 /PH6 /PH5 /PH4 /PH3 /PH2 /PH1 /PH0 • Bit 0 (/PH0) Control bit is used to enable the pull-high of P60 pin. 0: Enable internal pull-high 1: Disable int
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EM78P156N OTP ROM Setting the ROC to "1" will enable the status of R-option pins (P50 ∼P51) that are read by the controller. Clearing the ROC will disable the R-option function. If the R-option function is selected, user must connect the P51 pin or/and P50 pin to VSS with a 430K Ω external resistor (Rex). If the Rex is connected/disconnected, the status of P50 (P51) is read as "0"/"1". Refer to Fig. 8. • Bits 0~3,5 Not used. 9. IOCF (Interrupt Mask Register) 7 6 5 4 3 2 1 0 - - - -
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EM78P156N OTP ROM CLK=Fosc/4 is used if CLK bit is "1". If TCC signal source comes from external clock input, TCC is increased by 1 at every falling edge or rising edge of TCC pin. • The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even when the oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time
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EM78P156N OTP ROM R-option function is used, it is recommended that P50~P51 are used as output pins. When R-option is in enable state, P50~P51 must be programmed as input pins. Under R-option mode, the current/power consumption by Rex should be taken into the consideration to promote energy conservation. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5 and Port 6 are shown in the following Figures 6, 7(a), 7(b), and Figu
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EM78P156N OTP ROM PCRD P Q D R _ CLK PCWR Q C L P61~P67 P IOD PORT Q D R _ PDWR CLK Q C L 0 M U 1 X TIN PDRD P D Q R CLK _ C Q L NOTE: Pull-high (down) and Open-drain are not shown in the figure. Fig. 7(b) The Circuit of I/O Port and I/O Control Register for P61~P67 IOCE.1 P Q D R CLK Interrupt _ C Q L RE.1 ENI Instruction P T10 D Q R T11 P CLK Q D R _ C CLK Q L _ C Q L T17 DISI Instruction Interrupt (Wake-up from SLEEP) /SLEP Next Instruction (Wake-up from SLEEP) Fig. 7(c) Block Di
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EM78P156N OTP ROM Table 4 Usage of Port 6 Input Change Wake-up/Interrupt Function Usage of Port 6 input status changed Wake-up/Interrupt (I) Wake-up from Port 6 Input Status Change (II) Port 6 Input Status Change Interrupt (a) Before SLEEP 1. Read I/O Port 6 (MOV R6,R6) 1 1. Disable WDT (using very carefully) 2. Execute "ENI" 2. Read I/O Port 6 (MOV R6,R6) 3. Enable interrupt (Set IOCF.1) 3. Execute "ENI" or "DISI" 4. IF Port 6 change (interrupt) 4. Enable interrupt (Set IOCF.1) →
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EM78P156N OTP ROM 4.5 RESET and Wake-up 1. RESET A RESET is initiated by one of the following events- (1) Power on reset. (2) /RESET pin input "low", or (3) WDT time-out (if enabled). 1 The device is kept in a RESET condition for a period of approx. 18ms (one oscillator start-up timer period) after the reset is detected. Once the RESET occurs, the following functions are performed. Refer to Fig.9. • The oscillator is running, or will be started. • The Program Counter (R2) is set t
