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CY7C138, CY7C139
4K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
Features Functional Description
■ True Dual-Ported memory cells that enable simultaneous reads The CY7C138 and CY7C139 are high speed CMOS 4K x 8 and
of the same memory location 4K x 9 dual-port static RAMs. Various arbitration schemes are
included on the CY7C138/9 to handle situations when multiple
■ 4K x 8 organization (CY7C138)
processors access the same piece of data. Two ports are
provided permitting independent, asynchron
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CY7C138, CY7C139 Pin Configurations Figure 1. 68-Pin PLCC (Top View) \ 98 7 6 5 4 3 2 1 68 6766 65 646362 61 I/O 2L 10 60 A 5L I/O 3L A 11 59 4L I/O 4L A 12 58 3L I/O 5L A 13 57 2L GND A 14 56 1L I/O 6L 15 55 A 0L I/O 7L INT 16 54 L V CC BUSY 17 53 L CY7C138/9 GND 18 52 GND I/O 0R 19 51 M/S I/O BUSY 1R 20 50 R I/O 2R 49 21 INT R V CC A 48 0R 22 I/O 3R A 23 47 1R I/O 4R A 24 46 2R I/O 5R 25 45 A 3R I/O 6R 26 44 A 4R 2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43 Table 1. Pin Definitions Lef
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CY7C138, CY7C139 Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage........................................... >2001V Exceeding maximum ratings may impair the useful life of the (per MIL-STD-883, Method 3015) [5] device. These user guidelines are not tested. Latch-Up Current.................................................... >200 mA Storage Temperature ................................. –65 °C to +150 °C Operating Range Ambient Tempera
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CY7C138, CY7C139 Electrical Characteristics Over the Operating Range (continued) 7C138-35 7C138-55 7C139-35 7C139-55 Parameter Description Test Conditions Unit Min Max Min Max V Output HIGH Voltage V = Min., I = –4.0 mA 2.4 2.4 V OH CC OH V Output LOW Voltage V = Min., I = 4.0 mA 0.4 0.4 V OL CC OL V 2.2 2.2 V IH V Input LOW Voltage 0.8 0.8 V IL I Input Leakage Current GND < V < V –10 +10 –10 +10 μA IX I CC I Output Leakage Current Output Disabled, GND < V < V –10 +10 –10 +10 μA OZ O CC I Oper
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CY7C138, CY7C139 Figure 2. AC Test Loads and Waveforms 5V 5V R1 = 893 Ω R1 = 893 Ω R = 250 Ω TH OUTPUT OUTPUT OUTPUT C= 30 pF C = 30pF C= 5pF R2 = 347 Ω R2 = 347 Ω V = 1.4V TH (a) Normal Load (Load 1) (b) Thé venin Equivalent (Load 1) (c) Three-State Delay (Load 3) ALL INPUT PULSES OUTPUT 3.0V 90% 90% C= 30pF 10% 10% GND < 3 ns < 3ns Load (Load 2) [9] Switching Characteristics Over the Operating Range 7C138-15 7C138-25 7C138-35 7C138-55 7C139-15 7C139-25 7C139-35 7C139-55 Parameter Descriptio
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CY7C138, CY7C139 [9] Switching Characteristics Over the Operating Range (continued) 7C138-15 7C138-25 7C138-35 7C138-55 7C139-15 7C139-25 7C139-35 7C139-55 Parameter Description Unit Min Max Min Max Min Max Min Max t Data Hold From Write End 0 0 0 0 ns HD [11,12] t R/W LOW to High Z 10 15 20 25 ns HZWE [11,12] t R/W HIGH to Low Z 3 3 3 3 ns LZWE [13] t Write Pulse to Data Delay 30 50 60 70 ns WDD [13] t Write Data Valid to Read Data Valid 25 30 35 40 ns DDD [14] BUSY TIMING t BUSY LOW from Add
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CY7C138, CY7C139 Switching Waveforms (continued) SEM or CE t HZCE t ACE OE t HZOE t DOE t LZOE t LZCE DATA VALID DATA OUT t PU t PD I CC I SB [20, 21] Figure 5. Read Timing with Port-to-Port Delay (M/S = L) t WC ADDRESS R MATCH t PWE R/W R t t SD HD DATA VALID INR ADDRESS L MATCH t DDD DATA OUTL VALID t WDD Notes 16. R/W is HIGH for read cycle. 17. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads. 18. Address valid prior to or coincident
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CY7C138, CY7C139 Switching Waveforms (continued) t WC ADDRESS t SCE SEM OR CE t t AW HA t PWE R/W t t t SA SD HD DATA IN DATA VALID OE t t HZOE LZOE HIGH IMPEDANCE DATA OUT [22, 24, 25] Figure 7. Write Cycle No. 2: R/W Three-States Data I/Os (Either Port) t WC ADDRESS t t SCE HA SEM OR CE t AW t SA t PWE R/W t t SD HD DATA VALID DATA IN t t LZWE HZWE HIGH IMPEDANCE DATA OUT Notes 20. BUSY = HIGH for the writing port. 21. CE = CE = LOW. L R 22. The internal write time of the memory is defined
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CY7C138, CY7C139 Switching Waveforms (continued) t t AA OHA A –A VALID ADDRESS VALID ADDRESS 0 2 t AW t ACE t HA SEM t t SCE SOP t SD I/O 0 DATA VALID DATA VALID IN OUT t HD t t SA PWE R/W t t SWRD DOE t OE SOP WRITE CYCLE READ CYCLE [27, 28, 29] Figure 9. Timing Diagram of Semaphore Contention A –A 0L 2L MATCH R/W L SEM L t SPS A –A MATCH 0R 2R R/W R SEM R Notes 25. Data I/O pins enter high impedance when OE is held LOW during write. 26. CE = HIGH for the duration of the above timing (both
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CY7C138, CY7C139 Switching Waveforms (continued) t WC ADDRESS R MATCH t PWE R/W R t t SD HD DATA IN VALID R t PS ADDRESS L MATCH t BLA t BHA BUSY L t BDD t DDD DATA VALID OUTL t WDD Figure 11. Write Timing with Busy Input (M/S=LOW) t PWE R/W t t WB WH BUSY Notes 27. I/O = I/O = LOW (request semaphore); CE = CE = HIGH 0R 0L R L 28. Semaphores are reset (available to both ports) at cycle start. 29. If t is violated, the semaphore will definitely be obtained by one side or the other, but there
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CY7C138, CY7C139 Switching Waveforms (continued) CE Valid First: L ADDRESS L,R ADDRESS MATCH CE L t PS CE R t t BLC BHC BUSY R CE Valid First: R ADDRESS ADDRESS MATCH L,R CE R t PS CE L t t BLC BHC BUSY L [30] Figure 13. Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: t or t RC WC ADDRESS L ADDRESS MATCH ADDRESS MISMATCH t PS ADDRESS R t t BLA BHA BUSY R Right Address Valid First: t or t RC WC ADDRESS R ADDRESS MATCH ADDRESS MISMATCH t PS ADDRESS L t t BLA BHA BUS
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CY7C138, CY7C139 Switching Waveforms (continued) Figure 14. Interrupt Timing Diagrams Left Side Sets INT : R t WC ADDRESS WRITE FFF L t [31] HA CE L R/W L INT R t [32] INS Right Side Clears INT : R t RC ADDRESS READ FFF R CE R [32] t INR R/W R OE R INT R Right Side Sets INT : L t WC ADDRESS R WRITE FFE [31] t HA CE R R/W R INT L [32] t INS Left Side Clears INT : L t RC ADDRESS R READ FFE CE L [32] t INR R/W L OE L INT L Notes 31. t depends on which enable pin (CE or R/W ) is deasserted first
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CY7C138, CY7C139 Master/Slave Architecture A M/S pin is provided in order to expand the word width by config- The CY7C138/9 consists of an array of 4K words of 8/9 bits each uring the device as either a master or a slave. The BUSY output of dual-port RAM cells, I/O and address lines, and control signals of the master is connected to the BUSY input of the slave. This (CE, OE, R/W). These control pins permit independent access enables the device to interface to a master device with no for reads
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CY7C138, CY7C139 Table 3. Non-Contending Read/Write Inputs Outputs Operation CE R/W OE SEM I/O 0-7/8 H X X H High Z Power-Down H H L L Data Out Read Data in Semaphore X X H X High Z I/O Lines Disabled H X L Data In Write to Semaphore L H L H Data Out Read L L X H Data In Write L X X L Illegal Condition Table 4. Interrupt Operation Example (assumes BUSY =BUSY =HIGH) L R Left Port Right Port Function R/W CE OE A INT R/W CE OE A INT 0-11 0-11 Set Left INT X X X X L L L X FFE X Reset Left INT X
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CY7C138, CY7C139 Figure 15. Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT OUTPUT SOURCE CURRENT NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE vs. OUTPUT VOLTAGE vs. SUPPLY VOLTAGE 1.4 1.2 200 I CC 1.2 1.0 I 160 CC 1.0 I 0.8 SB3 I SB3 120 0.8 0.6 V = 5.0V CC V = 5.0V CC 0.6 80 T = 25°C V = 5.0V A IN 0.4 0.4 40 0.2 0.2 0 0.6 0.0 –55 25 125 0 1.0 2.0 3.0 4.0 5.0 4.0 4.5 5.0 5.5 6.0 AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V) SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME OUTPUT
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CY7C138, CY7C139 Ordering Information 4K x8 Dual-Port SRAM Speed Package Operating Ordering Code Package Type (ns) Name Range 15 CY7C138-15JC J81 68-Lead Plastic Leaded Chip Carrier Commercial CY7C138-15JXC J81 68-Lead Pb-Free Plastic Leaded Chip Carrier 25 CY7C138-25JC J81 68-Lead Plastic Leaded Chip Carrier Commercial CY7C138-25JXC J81 68-Lead Pb-Free Plastic Leaded Chip Carrier CY7C138-25JI J81 68-Lead Plastic Leaded Chip Carrier Industrial CY7C138-25JXI J81 68-Lead Pb-Free Plastic Leaded C
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CY7C138, CY7C139 Document History Page Document Title: CY7C138/CY7C139 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Document Number: 38-06037 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 110180 SZV 09/29/01 Change from Spec number: 38-00536 to 38-06037 *A 122287 RBI 12/27/02 Power up requirements added to Maximum Ratings Information *B 393403 YIM See ECN Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C138-15JXC, CY7C138-25JXC, CY7C139-25JXC *C
