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STK14C88-3
256 Kbit (32K x 8) AutoStore nvSRAM
Features Functional Description
■ 35 ns and 45 ns access times The Cypress STK14C88-3 is a 256 Kb fast static RAM with
a nonvolatile element in each memory cell. The embedded
■ Automatic nonvolatile STORE on power loss ™
nonvolatile elements incorporate QuantumTrap
technology producing the world’s most reliable nonvolatile
■ Nonvolatile STORE under Hardware or Software control
memory. The SRAM provides unlimited read and write
■ Automatic RECALL to
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STK14C88-3 Pin Configurations Figure 1. Pin Diagram - 32-Pin SOIC/32-Pin PDIP Table 1. Pin Definitions - 32-Pin SOIC/32-Pin PDIP Pin Name Alt IO Type Description A –A Input Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM. 0 14 DQ -DQ Input or Bidirectional Data IO lines. Used as input or output lines depending on operation. 0 7 Output Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the WE W IO pins is written to the specific address l
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STK14C88-3 Figure 2. AutoStore Mode Device Operation The STK14C88-3 nvSRAM is made up of two functional compo- nents paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation) or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture enables the storage and recall of all cells in parallel.
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STK14C88-3 and share a single capacitor. The capacitor size is scaled by Figure 3. AutoStore Inhibit Mode the number of devices connected to it. When any one of the STK14C88-3 detects a power loss and asserts HSB, the common HSB pin causes all parts to request a STORE cycle. (A STORE takes place in those STK14C88-3 that are written since the last nonvolatile cycle.) During any STORE operation, regardless of how it is initiated, the STK14C88-3 continues to drive the HSB pin LOW, releasing it onl
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STK14C88-3 Software RECALL Low Average Active Power Data is transferred from the nonvolatile memory to the SRAM by CMOS technology provides the STK14C88-3 the benefit of a software address sequence. A software RECALL cycle is drawing significantly less current when it is cycled at times longer initiated with a sequence of READ operations in a manner similar than 50 ns. Figure 4 and Figure 5 show the relationship between to the software STORE initiation. To initiate the RECALL cycle, I and READ o
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STK14C88-3 system manufacturing test to ensure these system routines Best Practices work consistently. Power up boot firmware routines should nvSRAM products have been used effectively for over 15 rewrite the nvSRAM into the desired state. While the years. While ease-of-use is one of the product’s main system nvSRAM is shipped in a preset state, best practice is to again values, experience gained working with hundreds of applica- rewrite the nvSRAM into the desired state as a safeguard tions ha
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STK14C88-3 Voltage on DQ or HSB .......................–0.5V to Vcc + 0.5V Maximum Ratings 0-7 Power Dissipation ......................................................... 1.0W Exceeding maximum ratings may shorten the useful life of the DC output Current (1 output at a time, 1s duration) .... 15 mA device. These user guidelines are not tested. Operating Range Storage Temperature ................................. –65 °C to +150 °C Range Ambient Temperature V Temperature under bias................
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STK14C88-3 Data Retention and Endurance Parameter Description Min Unit DATA Data Retention 100 Years R NV Nonvolatile STORE Operations 1,000 K C Capacitance [8] In the following table, the capacitance parameters are listed. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25 °C, f = 1 MHz, 5pF IN A V = 0 to 3.0 V CC C Output Capacitance 7 pF OUT Thermal Resistance [8] In the following table, the thermal resistance parameters are listed. Parameter Description Test Conditions
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STK14C88-3 AC Switching Characteristics SRAM Read Cycle Parameter 35 ns 45 ns Description Unit Cypress Alt Min Max Min Max Parameter t t Chip Enable Access Time 35 45 ns ACE ELQV [9] t t t Read Cycle Time 35 45 ns RC AVAV, ELEH [10] t t Address Access Time 35 45 ns AA AVQV t t Output Enable to Data Valid 15 20 ns DOE GLQV [10] t t Output Hold After Address Change 5 5 ns OHA AXQX [11] t t Chip Enable to Output Active 5 5 ns LZCE ELQX [11] t t Chip Disable to Output Inactive 13 15 ns HZCE EHQZ [
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STK14C88-3 Table 3. SRAM Write Cycle Parameter 35 ns 45 ns Description Unit Cypress Alt Min Max Min Max Parameter t t Write Cycle Time 35 45 ns WC AVAV t t t Write Pulse Width 25 30 ns PWE WLWH, WLEH t t t Chip Enable To End of Write 25 30 ns SCE ELWH, ELEH t t t Data Setup to End of Write 12 15 ns SD DVWH, DVEH t t t Data Hold After End of Write 0 0 ns HD WHDX, EHDX t t t Address Setup to End of Write 25 30 ns AW AVWH, AVEH t t t Address Setup to Start of Write 0 0 ns SA AVWL, AVEL t t t Addr
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STK14C88-3 AutoStore or Power Up RECALL STK14C88-3 Parameter Alt Description Unit Min Max [15] t t Power up RECALL Duration 550 μs HRECALL RESTORE [16, 17] t t STORE Cycle Duration 10 ms STORE HLHZ [16] t Low Voltage Trigger (V ) to HSB low 300 ns VSBL SWITCH V Low Voltage Reset Level 2.4 V RESET V Low Voltage Trigger Level 2.7 2.95 V SWITCH [16] t t Time Allowed to Complete SRAM Cycle 1 μs DELAY BLQZ Switching Waveforms Figure 11. AutoStore/Power Up RECALL WE Notes 15. t starts from the time
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STK14C88-3 Software Controlled STORE/RECALL Cycle [18, 19] The software controlled STORE/RECALL cycle follows. 35 ns 45 ns Parameter Alt Description Unit Min Max Min Max [16] t t STORE/RECALL Initiation Cycle Time 35 45 ns RC AVAV [18, 19] t t Address Setup Time 0 0 ns SA AVEL [18, 19] t t Clock Pulse Width 25 30 ns CW ELEH [18, 19] t t Address Hold Time 20 20 ns HACE ELAX RECALL Duration 20 20 μs t RECALL Switching Waveforms [19] Figure 12. CE Controlled Software STORE/RECALL Cycle t t RC R
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STK14C88-3 Hardware STORE Cycle STK14C88-3 Parameter Alt Description Unit Min Max t t Hardware STORE Pulse Width 15 ns PHSB HLHX [16, 20] t t t Hardware STORE High to Inhibit Off 700 ns DHSB RECOVER, HHQX t Hardware STORE Low to STORE Busy 300 ns HLBL Switching Waveforms Figure 13. Hardware STORE Cycle Note 20. t is only applicable after t is complete. DHSB STORE Document Number: 001-50592 Rev. ** Page 13 of 17 [+] Feedback
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STK14C88-3 Part Numbering Nomenclature STK14C88- 3N F 45 I TR Packaging Option: TR = Tape and Reel Blank = Tube Temperature Range: Blank - Commercial (0 to 70°C) I - Industrial (-40 to 85°C) Speed: 35 - 35 ns 45 - 45 ns Lead Finish F = 100% Sn (Matte Tin) Package: N = Plastic 32-pin 300 mil SOIC W = Plastic 32-pin 600 mil DIP Ordering Information Speed Operating Ordering Code Package Diagram Package Type (ns) Range 35 STK14C88-3NF35TR 51-85127 32-pin SOIC Commercial STK14C88-3NF35 51-85127 32-p
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STK14C88-3 Package Diagrams Figure 14. 32-Pin (300 Mil) SOIC (51-85127) PIN 1 ID 16 1 MIN. DIMENSIONS IN INCHES[MM] 0.292[7.416] 0.299[7.594] MAX. 0.405[10.287] REFERENCE JEDEC MO-119 0.419[10.642] PART # 17 32 S32.3 STANDARD PKG. SZ32.3 LEAD FREE PKG. SEATING PLANE 0.810[20.574] 0.822[20.878] 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.050[1.270] 0.006[0.152] 0.026[0.660] 51-85058 *A 0.021[0.533] TYP. 0.012[0.304] 0.032[0.812] 0.041[1.041] 0.004[0.101] 0.0100[0.254] 0.014[0.355] 0.020[0.508] 51-8
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STK14C88-3 Package Diagrams (continued) Figure 15. 32-Pin (600 Mil) PDIP (51-85018) 51-85018-*A Document Number: 001-50592 Rev. ** Page 16 of 17 [+] Feedback
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STK14C88-3 Document History Page Document Title: STK14C88-3 256 Kbit (32K x 8) AutoStore nvSRAM Document Number: 001-50592 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 2625096 GVCH/PYRS 12/19/08 New data sheet Sales, Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Produ
