Resumo do conteúdo contido na página número 1
®
Intel Core™ i7 Processor Family for
LGA2011 Socket
Datasheet – Volume 1 of 2
®
Supporting Desktop Intel Core™ i7-4960X Extreme Edition Processor
Series for the LGA2011 Socket
®
Supporting Desktop Intel Core™ i7-49xx and i7-48xx Processor Series
for the LGA2011 Socket
September 2013
329366-001
Resumo do conteúdo contido na página número 2
® INFORMA S UNLES ALE AND/OR USE OF INTEL PRODUCT S O TION THERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCT IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH Intel S INCLUDING LIABILITY OR WARRANTIES RELA S ARE NO PRODUCT T DESIGNED NOR INTENDED FOR ANY APPLICA TING T S. NO LICENSE, Express* OR IMPLIED O FITNESS FOR A PARTICULAR PURPOSE, MERCHANT , BY EST TION IN WHICH THE OPPEL OR O ABILI THERWISE, T TY FAILURE OF THE INTEL PRODUCT COULD CREA , OR INFRINGEMENT OF ANY P O ANY INTELLECTUAL PR
Resumo do conteúdo contido na página número 3
Table of Contents 1 Introduction ..............................................................................................................8 1.1 Processor Feature Details .....................................................................................9 1.2 Supported Technologies .....................................................................................10 1.3 Interfaces ........................................................................................................10 1
Resumo do conteúdo contido na página número 4
4.2 Processor Core / Package Power Management ...................................................... 32 ® ® 4.2.1 Enhanced Intel SpeedStep Technology ................................................. 32 4.2.2 Low-Power Idle States............................................................................ 33 4.2.3 Requesting Low-Power Idle States ........................................................... 34 4.2.4 Core C-states ....................................................................
Resumo do conteúdo contido na página número 5
Figures 1-1 Processor Platform Block Diagram Example.............................................................9 1-2 PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2) ..................12 2-1 PCI Express* Layering Diagram...........................................................................19 2-2 Packet Flow through the Layers...........................................................................19 4-1 Idle Power Management Breakdown of the Processor Cores........
Resumo do conteúdo contido na página número 6
7-10 Voltage Specifications........................................................................................ 63 7-11 Current Specifications........................................................................................ 65 7-12 V Overshoot Specifications.............................................................................. 66 CC 7-13 DDR3 and DDR3L Signal DC Specifications ........................................................... 67 7-14 PECI DC Specifications ..........
Resumo do conteúdo contido na página número 7
Revision History Revision Description Date Number 001 • Initial release September 2013 § Datasheet 7
Resumo do conteúdo contido na página número 8
Introduction 1 Introduction ® The Intel Core™ i7 processor family for LGA2011 socket are the next generation of 64-bit, multi-core desktop processors built on 22-nanometer process technology. Based ® on the low-power/high-performance Intel Core™ i7 processor micro-architecture, the processor is designed for a two-chip platform instead of to the traditional three-chip platforms (processor, Memory Controller Hub, and Platform Controller Hub). The two- chip platform consists of a processor an
Resumo do conteúdo contido na página número 9
Introduction Figure 1-1. Processor Platform Block Diagram Example 1.1 Processor Feature Details • Up to 6 execution cores ® • Each core supports two threads (Intel Hyper-Threading Technology), up to 12 threads per socket • 32KB instruction and 32-KB data first-level cache (L1) for each core • 256KB shared instruction/data mid-level (L2) cache for each core • Up to 15MB last level cache (LLC): up to 2.5MB per core instruction/data last level cache (LLC), shared among all cores Datasheet 9
Resumo do conteúdo contido na página número 10
Introduction 1.2 Supported Technologies ® ® • Intel Virtualization Technology (Intel VT) ® ® ® • Intel Virtualization Technology (Intel VT) for Directed I/O (Intel VT-d) ® ® • Intel Virtualization Technology (Intel VT) Processor Extensions ® • Intel 64 Architecture ® ® • Intel Streaming SIMD Extensions 4.1 (Intel SSE4.1) ® ® • Intel Streaming SIMD Extensions 4.2 (Intel SSE4.2) ® ® • Intel Advanced Vector Extensions (Intel AVX) ® • Intel AVX Floating Point Bit Depth Conversion (Float 16) ® • I
Resumo do conteúdo contido na página número 11
Introduction 1.3.2 PCI Express* • The PCI Express* port(s) are fully-compliant with the PCI Express* Base Specification, Revision 3.0 (PCIe 3.0) • Support for PCI Express* 3.0 (8.0 GT/s), 2.0 (5.0 GT/s), and 1.0 (2.5 GT/s) • Up to 40 lanes of PCI Express* interconnect for general purpose PCI Express* devices at PCIe* 3.0 speeds that are configurable for up to 10 independent ports • 4 lanes of PCI Express* at PCIe* 2.0 speeds when not using DMI2 port (Port 0), also can be downgraded to x2 or
Resumo do conteúdo contido na página número 12
Introduction Figure 1-2. PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2) 1.3.3 Direct Media Interface Gen 2 (DMI2) • Serves as the chip-to-chip interface to the PCH • The DMI2 port supports x4 link width and only operates in a x4 mode when in DMI2 • Operates at PCI Express* 1.0 or 2.0 speeds • Transparent to software • Processor and peer-to-peer writes and reads with 64-bit address support • APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined “End
Resumo do conteúdo contido na página número 13
Introduction 1.3.4 Platform Environment Control Interface (PECI) The PECI is a one-wire interface that provides a communication channel between a PECI client (the processor) and a PECI master (the PCH). Refer to the Processor Thermal Mechanical Specifications and Design Guide for additional details on PECI services available in the processor (Refer to the Related Documents section). • Supports operation at up to 2 Mbps data transfers • Link layer improvements to support additional services
Resumo do conteúdo contido na página número 14
Introduction 1.6 Package Summary The processor socket type is noted as LGA2011. The processor package is a 52.5 x 45 mm FC-LGA package (LGA2011). Refer to the Processor Thermal Mechanical Specification and Design Guide (see Related Documents section) for the package mechanical specifications. 1.7 Terminology Table 1-1. Terminology (Sheet 1 of 3) Term Description ACPI Advanced Configuration and Power Interface ASPM Active State Power Management CCM Continuous Conduction Mode DCM Discontinuo
Resumo do conteúdo contido na página número 15
Introduction Table 1-1. Terminology (Sheet 2 of 3) Term Description ® ® Intel Virtualization Technology (Intel VT) for Directed I/O. Intel VT-d is a hardware assist, under system software (Virtual Machine Manager or operating system) ® Intel VT-d control, for enabling I/O device virtualization. Intel VT-d also brings robust security by providing protection from errant DMAs by using DMA remapping, a key feature of Intel VT-d. IOV I/O Virtualization Jitter Any timing variation of a transitio
Resumo do conteúdo contido na página número 16
Introduction Table 1-1. Terminology (Sheet 3 of 3) Term Description TSOD Thermal Sensor on DIMM UDIMM Unbuffered Dual In-line Module Uncore The portion of the processor comprising the shared cache, IMC, HA, PCU, and UBox. Signaling convention that is binary and unidirectional. In this binary signaling, one bit is sent for every edge of the forwarded clock, whether it be a rising edge or a falling edge. If a number of edges are collected at instances t , t , t ,...., t then the UI at Unit In
Resumo do conteúdo contido na página número 17
Introduction Table 1-3. Public Specifications Document Document Number / Location Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info PCI Local Bus Specification 3.0 http://www.pcisig.com/specifications PCI Express Base Specification - Revision 2.1 and 1.1 http://www.pcisig.com PCI Express Base Specification - Revision 3.0 System Management Bus (SMBus) Specification, Revision 2.0 http://smbus.org/ DDR3 SDRAM Specification http://www.jedec.org Low (JESD22-A119) an
Resumo do conteúdo contido na página número 18
Interfaces 2 Interfaces This chapter describes the functional behaviors supported by the processor. Topics covered include: • System Memory Interface • PCI Express* Interface • Direct Media Interface 2 (DMI2) / PCI Express* Interface • Platform Environment Control Interface (PECI) 2.1 System Memory Interface 2.1.1 System Memory Technology Support The Integrated Memory Controller (IMC) supports DDR3 protocols with four independent 64-bit memory channels and supports 1 unbuffered DIMM per chan
Resumo do conteúdo contido na página número 19
Interfaces 2.2 PCI Express* Interface This section describes the PCI Express* 3.0 interface capabilities of the processor. See the PCI Express* Base Specification for details of PCI Express* 3.0. 2.2.1 PCI Express* Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged. The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-and-Play specification. The PCI Express* architectu
Resumo do conteúdo contido na página número 20
Interfaces 2.2.1.1 Transaction Layer The upper layer of the PCI Express* architecture is the Transaction Layer. The Transaction Layer's primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as well as certain types of events. The Transaction Layer also manages flow control of TLPs. 2.2.1.2 Data Link Layer The middle layer in the PCI Express* stack, the Data Link Layer, serves as an int
