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TMS320C674x/OMAP-L1x Processor
Ethernet Media Access Controller (EMAC)/
Management Data Input/Output (MDIO) Module
User's Guide
Literature Number: SPRUFL5B
April 2011
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2 SPRUFL5B–April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated
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Preface ...................................................................................................................................... 10 1 Introduction ...................................................................................................................... 12 1.1 Purpose of the Peripheral ............................................................................................. 12 1.2 Features .............................................................................
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www.ti.com (C0RXIMAX-C2RXIMAX) ............................................................................................. 68 3.13 EMAC Control Module Interrupt Core Transmit Interrupts Per Millisecond Registers (C0TXIMAX-C2TXIMAX) .............................................................................................. 69 4 MDIO Registers ................................................................................................................. 70 4.1 MDIO Revision ID Register (REV
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www.ti.com 5.31 Emulation Control Register (EMCONTROL) ...................................................................... 114 5.32 FIFO Control Register (FIFOCONTROL) ......................................................................... 114 5.33 MAC Configuration Register (MACCONFIG) ..................................................................... 115 5.34 Soft Reset Register (SOFTRESET) ................................................................................ 115 5.35 MAC So
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www.ti.com List of Figures 1 EMAC and MDIO Block Diagram........................................................................................ 13 2 Ethernet Configuration—MII Connections.............................................................................. 15 3 Ethernet Configuration—RMII Connections............................................................................ 16 4 Ethernet Frame Format......................................................................................
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www.ti.com 47 Transmit Interrupt Mask Set Register (TXINTMASKSET) ........................................................... 92 48 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ..................................................... 93 49 MAC Input Vector Register (MACINVECTOR) ........................................................................ 94 50 MAC End Of Interrupt Vector Register (MACEOIVECTOR)......................................................... 95 51 Receive Interrupt
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www.ti.com List of Tables 1 EMAC and MDIO Signals for MII Interface............................................................................. 15 2 EMAC and MDIO Signals for RMII Interface........................................................................... 16 3 Ethernet Frame Description.............................................................................................. 17 4 Basic Descriptor Description...........................................................................
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www.ti.com 46 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ..................................... 92 47 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions............................... 93 48 MAC Input Vector Register (MACINVECTOR) Field Descriptions.................................................. 94 49 MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions................................... 95 50 Receive Interrupt Status (Unmask
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Preface SPRUFL5B–April 2011 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the device. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and the registers description for each module. Notational Conventions This document uses
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www.ti.com Related Documentation From Texas Instruments SPRUGM7 — OMAP-L138 Applications Processor System Reference Guide. Describes the System-on-Chip (SoC) including the ARM subsystem, DSP subsystem, system memory, device clocking, phase-locked loop controller (PLLC), power and sleep controller (PSC), power management, ARM interrupt controller (AINTC), and system configuration module. SPRUFK9 — TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide. Provides an overview and briefl
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User's Guide SPRUFL5B–April 2011 EMAC/MDIO Module 1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the device. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and a description of the registers for each module. The EMAC controls the flow of pac
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www.ti.com Introduction 1.3 Functional Block Diagram Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral: • EMAC control module • EMAC module • MDIO module The EMAC control module is the main interface between the device core processor to the EMAC and MDIO modules. The EMAC control module controls device interrupts and incorporates an 8k-byte internal RAM to hold EMAC buffer descriptors (also known as CPPI RAM). The MDIO module implements the 802.3 serial management inte
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Architecture www.ti.com 1.4 Industry Standard(s) Compliance Statement The EMAC peripheral conforms to the IEEE 802.3 standard, describing the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. The IEEE 802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E). However, the EMAC deviates from the standard in the way it handles transmit underflow errors. The EMAC MII interface does not use the Transmit
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www.ti.com Architecture The individual EMAC and MDIO signals for the MII interface are summarized in Table 1. For more information, refer to either the IEEE 802.3 standard or ISO/IEC 8802-3:2000(E). Figure 2. Ethernet Configuration—MII Connections MII_TXCLK MII_TXD[3−0] 2.5 MHz MII_TXEN or 25 MHz MII_COL MII_CRS Physical System layer MII_RXCLK Transformer core device MII_RXD[3−0] (PHY) MII_RXDV MII_RXER RJ−45 MDIO_CLK MDIO_D Table 1. EMAC and MDIO Signals for MII Interface Signal Type Descriptio
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Architecture www.ti.com Table 1. EMAC and MDIO Signals for MII Interface (continued) Signal Type Description MDIO_CLK O Management data clock (MDIO_CLK). The MDIO data clock is sourced by the MDIO module on the system. It is used to synchronize MDIO data access operations done on the MDIO pin. The frequency of this clock is controlled by the CLKDIV bits in the MDIO control register (CONTROL). MDIO_D I/O Management data input output (MDIO_D). The MDIO data pin drives PHY management data into and
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www.ti.com Architecture 2.4 Ethernet Protocol Overview A brief overview of the Ethernet protocol is given in the following subsections. See the IEEE 802.3 standard document for in-depth information on the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method. 2.4.1 Ethernet Frame Format All the Ethernet technologies use the same frame structure. The format of an Ethernet frame is shown in Figure 4 and described in Table 3. The Ethernet packet, which is the collection of
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Architecture www.ti.com 2.4.2 Ethernet’s Multiple Access Protocol Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel -- when an EMAC port transmits a frame, all the adapters on the local network receive the frame. Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms are used when the EMAC operates in half-duplex mode. When operating in full-duplex mode, there is no contention for use of a shared medium because there are exactly two ports on t
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www.ti.com Architecture Table 4. Basic Descriptor Description Word Offset Field Field Description 0 Next Descriptor The next descriptor pointer is used to create a single linked list of descriptors. Each descriptor Pointer describes a packet or a packet fragment. When a descriptor points to a single buffer packet or the first fragment of a packet, the start of packet (SOP) flag is set in the flags field. When a descriptor points to a single buffer packet or the last fragment of a packet, the end
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Architecture www.ti.com 2.5.2 Transmit and Receive Descriptor Queues The EMAC module processes descriptors in linked lists as discussed in Section 2.5.1. The lists used by the EMAC are maintained by the application software through the use of the head descriptor pointer registers (HDP). The EMAC supports eight channels for transmit and eight channels for receive. The corresponding head descriptor pointers are: • TXnHDP - Transmit Channel n DMA Head Descriptor Pointer Register • RXnHDP - Receive
