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PRELIMINARY
CY14B102L, CY14B102N
2 Mbit (256K x 8/128K x 16) nvSRAM
Features Functional Description
■ 20 ns, 25 ns, and 45 ns Access Times The Cypress CY14B102L/CY14B102N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
■ Internally organized as 256K x 8 (CY14B102L) or 128K x 16
organized as 256K bytes of 8 bits each or 128K words of 16 bits
(CY14B102N)
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most relia
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PRELIMINARY CY14B102L, CY14B102N Pinouts Figure 1. Pin Diagram - 48 FBGA 48-FBGA 48-FBGA (x8) (x16) Top View Top View (not to scale) (not to scale) 1 2 3 4 5 6 1 2 3 4 5 6 A A A NC A BLE OE OE A A NC 0 1 2 A NC 0 1 2 A DQ8 BHE A A NC A A CE DQ0 B NC CE NC B 3 4 3 4 A A C C DQ9 DQ10 DQ1 DQ2 DQ0 A A NC DQ4 5 6 NC 5 6 [4] A V V V A V SS DQ11 7 DQ3 CC D A DQ5 CC D NC SS DQ1 7 17 V A V V A V V DQ4 E V E CC DQ12 16 SS CC DQ2 16 DQ6 SS CAP CAP F F DQ14 DQ13 A A DQ3 NC A A DQ5 DQ6 NC DQ7 14 15 14 15
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PRELIMINARY CY14B102L, CY14B102N Pinouts (continued) Figure 3. Pin Diagram - 54 Pin TSOP II (x16) NC 54 HSB 1 [6] [5] NC 53 NC 2 [4] A 52 0 3 NC A 51 A 1 4 16 A 50 A 2 5 15 49 A OE 3 6 A 48 BHE 4 7 47 CE BLE 8 DQ0 46 DQ15 9 DQ1 45 10 DQ14 (x16) 44 DQ2 11 DQ13 (Not to Scale) DQ3 43 DQ12 12 V 42 CC V 13 SS V 41 V SS 14 CC 40 DQ4 DQ11 15 39 DQ5 DQ10 16 38 DQ6 DQ9 17 37 DQ8 DQ7 18 36 WE V 19 CAP 35 A A 5 20 14 34 A A 6 21 13 33 A A 22 12 7 32 A A 23 11 8 31 A 24 A 10 9 30 NC 25 NC 29 26 NC NC 27 2
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PRELIMINARY CY14B102L, CY14B102N Figure 4 shows the proper connection of the storage capacitor Device Operation (V ) for automatic store operation. Refer to DC Electrical CAP The CY14B102L/CY14B102N nvSRAM is made up of two Characteristics on page 7 for the size of V . The voltage on CAP functional components paired in the same physical cell. They are the V pin is driven to V by a regulator on the chip. A pull CAP CC an SRAM memory cell and a nonvolatile QuantumTrap cell. The up should be place
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PRELIMINARY CY14B102L, CY14B102N completion of the STORE operation, the The software sequence may be clocked with CE controlled reads CY14B102L/CY14B102N remains disabled until the HSB pin or OE controlled reads. After the sixth address in the sequence returns HIGH. Leave the HSB unconnected if it is not used. is entered, the STORE cycle commences and the chip is disabled. HSB will be driven LOW. It is important to use read Hardware RECALL (Power Up) cycles and not write cycles in the sequence,
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PRELIMINARY CY14B102L, CY14B102N Table 1. Mode Selection (continued) [8] [3] A - A Mode IO Power CE WE OE, BHE, BLE 15 0 [9, 10] L H L 0x4E38 Read SRAM Output Data Active 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4B46 AutoStore Enable Output Data [9, 10] L H L 0x4E38 Read SRAM Output Data Active I CC2 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8
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PRELIMINARY CY14B102L, CY14B102N Package Power Dissipation Maximum Ratings Capability (T = 25°C) ................................................... 1.0W A Exceeding maximum ratings may impair the useful life of the Surface Mount Pb Soldering device. These user guidelines are not tested. Temperature (3 Seconds).......................................... +260°C Storage Temperature ................................. –65°C to +150°C DC Output Current (1 output at a time, 1s duration).... 15 mA Maxim
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PRELIMINARY CY14B102L, CY14B102N Data Retention and Endurance Parameter Description Min Unit DATA Data Retention 20 Years R NV Nonvolatile STORE Operations 200 K C Capacitance [14] In the following table, the capacitance parameters are listed. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25°C, f = 1 MHz, 7pF IN A V = 0 to 3.0V CC C Output Capacitance 7 pF OUT Thermal Resistance [14] In the following table, the thermal resistance parameters are listed. Parameter Descrip
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PRELIMINARY CY14B102L, CY14B102N AC Switching Characteristics Parameters 20 ns 25 ns 45 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameters Parameters SRAM Read Cycle t t Chip Enable Access Time 20 25 45 ns ACE ACS [15] t t Read Cycle Time 20 25 45 ns RC RC [16] t t Address Access Time 20 25 45 ns AA AA t t Output Enable to Data Valid 10 12 20 ns DOE OE [16] t t Output Hold After Address Change 3 3 3 ns OHA OH [17] t t Chip Enable to Output Active 3 3 3 ns LZCE LZ [17] t t Chip D
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PRELIMINARY CY14B102L, CY14B102N [3, 15, 19] Figure 7. SRAM Read Cycle #2: CE and OE Controlled [3, 18, 19, 20] Figure 8. SRAM Write Cycle #1: WE Controlled Notes 20. CE or WE must be >V during address transitions. IH Document #: 001-45754 Rev. *B Page 10 of 24 [+] Feedback
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PRELIMINARY CY14B102L, CY14B102N [3, 18, 19, 20] Figure 9. SRAM Write Cycle #2: CE Controlled [3, 18, 19, 20] Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled Document #: 001-45754 Rev. *B Page 11 of 24 [+] Feedback
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PRELIMINARY CY14B102L, CY14B102N AutoStore/Power Up RECALL 20 ns 25 ns 45 ns Parameters Description Unit Min Max Min Max Min Max [21] t Power Up RECALL Duration 20 20 20 ms HRECALL [22] t STORE Cycle Duration 8 8 8 ms STORE [23] t Time Allowed to Complete SRAM Cycle 20 25 25 ns DELAY V Low Voltage Trigger Level 2.65 2.65 2.65 V SWITCH t VCC Rise Time 150 150 150 μs VCCRISE [14] V HSB Output Driver Disable Voltage 1.9 1.9 1.9 V HDIS t HSB To Output Active Time 5 5 5 μs LZHSB t HSB High Active
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PRELIMINARY CY14B102L, CY14B102N Software Controlled STORE/RECALL Cycle [26, 27] In the following table, the software controlled STORE/RECALL cycle parameters are listed. 20 ns 25 ns 45 ns Parameters Description Unit Min Max Min Max Min Max t STORE/RECALL Initiation Cycle Time 20 25 45 ns RC t Address Setup Time 0 0 0 ns SA t Clock Pulse Width 15 20 30 ns CW t Address Hold Time 0 0 0 ns HA t RECALL Duration 200 200 200 μs RECALL Switching Waveforms [27] Figure 12. CE and OE Controlled Software
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PRELIMINARY CY14B102L, CY14B102N Hardware STORE Cycle 20 ns 25 ns 45 ns Parameters Description Unit Min Max Min Max Min Max t HSB To Output Active Time when write latch not set 20 25 25 ns DHSB t Hardware STORE Pulse Width 15 15 15 ns PHSB [28, 29] t Soft Sequence Processing Time 100 100 100 μs SS Switching Waveforms [22] Figure 14. Hardware STORE Cycle [28, 29] Figure 15. Soft Sequence Processing N
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PRELIMINARY CY14B102L, CY14B102N Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations. For x8 Configuration [2] CE WE OE Inputs/Outputs Mode Power H X X High Z Deselect/Power down Standby L H L Data Out (DQ –DQ ); Read Active 0 7 L H H High Z Output Disabled Active L L X Data in (DQ –DQ ); Write Active 0 7 For x16 Configuration [2] CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High-Z Deselect/Power down Standby L X X H H High-Z Output Disabled Active L H L L L
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PRELIMINARY CY14B102L, CY14B102N Ordering Information Speed Package Operating Ordering Code Package Type (ns) Diagram Range 20 CY14B102L-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14B102L-ZS20XIT 51-85087 44-pin TSOP II Industrial CY14B102L-ZS20XI 51-85087 44-pin TSOP II CY14B102L-ZS20XAT 51-85087 44-pin TSOP II Automotive CY14B102L-BA20XCT 51-85128 48-ball FBGA Commercial CY14B102L-BA20XIT 51-85128 48-ball FBGA Industrial CY14B102L-BA20XI 51-85128 48-ball FBGA CY14B102L-BA20XAT 51-85128 48-ba
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PRELIMINARY CY14B102L, CY14B102N Ordering Information (continued) Speed Package Operating Ordering Code Package Type (ns) Diagram Range 25 CY14B102L-ZS25XCT 51-85087 44-pin TSOP II Commercial CY14B102L-ZS25XIT 51-85087 44-pin TSOP II Industrial CY14B102L-ZS25XI 51-85087 44-pin TSOP II CY14B102L-ZS25XAT 51-85087 44-pin TSOP II Automotive CY14B102N-BA25XCT 51-85128 48-ball FBGA Commercial CY14B102L-BA25XIT 51-85128 48-ball FBGA Industrial CY14B102L-BA25XI 51-85128 48-ball FBGA CY14B102N-BA25XAT 51
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PRELIMINARY CY14B102L, CY14B102N Ordering Information (continued) Speed Package Operating Ordering Code Package Type (ns) Diagram Range 45 CY14B102L-ZS45XCT 51-85087 44-pin TSOP II Commercial CY14B102L-ZS45XIT 51-85087 44-pin TSOP II Industrial CY14B102L-ZS45XI 51-85087 44-pin TSOP II CY14B102L-ZS45XAT 51-85087 44-pin TSOP II Automotive CY14B102L-BA45XCT 51-85128 48-ball FBGA Commercial CY14B102L-BA45XIT 51-85128 48-ball FBGA Industrial CY14B102L-BA45XI 51-85128 48-ball FBGA CY14B102L-BA45XAT 5
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PRELIMINARY CY14B102L, CY14B102N Part Numbering Nomenclature CY 14 B 102 L - ZS P 20 X C T Option: Temperature: T - Tape & Reel I - Industrial (–40 to 85°C) Blank - Std. C - Commercial (0 to 70°C) Speed: A - Automotive (-40 to +125°C) Pb-Free 20 - 20ns 25 - 25ns 45 - 45 ns Package: P - 54 Pin Blank - 44 Pin BA - 48 FBGA Data Bus: ZS - TSOP II L - x8 N - x16 Density: 102 - 2 Mb Voltage: B - 3.0V NVSRAM 14 - Auto Store + Software Store + Hardware Store Cypress Document #: 001-45754 Rev. *B Page
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PRELIMINARY CY14B102L, CY14B102N Package Diagrams Figure 16. 44-Pin TSOP II (51-85087) DIMENSION IN MM (INCH) MAX MIN. PIN 1 I.D. 22 1 R O E K A X S G 23 44 EJECTOR PIN TOP VIEW BOTTOM VIEW 10.262 (0.404) 0.400(0.016) 0.800 BSC 10.058 (0.396) 0.300 (0.012) BASE PLANE (0.0315) 0.210 (0.0083) 0°-5° 0.120 (0.0047) 0.10 (.004) 18.517 (0.729) 0.597 (0.0235) 18.313 (0.721) 0.406 (0.0160) SEATING PLANE 51-85087-*A Document #: 001-45754 Rev. *B Page 20 of 24 [+] Feedback 1.194 (0.047) 0.991 (0.039)
