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®
CY62167E MoBL
16-Mbit (1M x 16 / 2M x 8) Static RAM
(CE HIGH, or CE LOW, or both BHE and BLE are HIGH).
Features
1 2
The input and output pins (IO through IO ) are placed in a
0 15
• Configurable as 1M x 16 or as 2M x 8 SRAM high impedance state when:
• Very high speed: 45 ns • The device is deselected (CE HIGH or CE LOW)
1 2
• Wide voltage range: 4.5V–5.5V • Outputs are disabled (OE HIGH)
• Ultra low standby power • Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH) or
—
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® CY62167E MoBL [2, 3] Pin Configuration 48-Pin TSOP I Top View A15 1 48 A16 A14 2 47 BYTE A13 3 46 Vss A12 4 45 IO15/A20 A11 5 44 IO7 A10 6 43 IO14 A9 7 42 IO6 A8 8 41 IO13 A19 9 40 IO5 10 39 NC IO12 11 38 IO4 WE CE 12 37 Vcc 2 13 36 NC IO11 14 35 BHE IO3 15 34 BLE IO10 A18 16 33 IO2 17 32 IO9 A17 18 31 A7 IO1 A6 19 30 IO8 20 29 A5 IO0 21 28 A4 OE 22 27 Vss A3 A2 23 26 CE1 24 25 A1 A0 Product Portfolio Power Dissipation Speed Product V Range (V) Operating I (mA) CC CC (ns) Standby I ( µA) SB
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® CY62167E MoBL [5, 6] DC Input Voltage ........................................–0.5V to 6.0V Maximum Ratings Output Current into Outputs (LOW) ............................ 20 mA Exceeding the maximum ratings may shorten the battery life Static Discharge Voltage........................................... >2001V of the device. User guidelines are not tested. (MIL-STD-883, Method 3015) Storage Temperature ................................–65°C to + 150°C Latch Up Current ...........................
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® CY62167E MoBL AC Test Loads and Waveforms ALL INPUT PULSES R1 V V CC CC 90% 90% OUTPUT 10% 10% GND FALL TIME= 1 V/ns R2 30 pF RISE TIME= 1 V/ns INCLUDING JIG AND EQUIVALENT TO: THÉVENIN EQUIVALENT SCOPE R TH OUTPUT V Parameters Values Unit R1 1800 Ω R2 990 Ω R 639 Ω TH V 1.77 V TH Data Retention Characteristics Over the Operating Range [4] Parameter Description Conditions Min Typ Max Unit V V for Data Retention 2.0 V DR CC [9] I Data Retention Current V = V 12 µA CCDR CC DR CE > V – 0.2V, CE
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® CY62167E MoBL Switching Characteristics [13, 14] Over the Operating Range 45 ns Parameter Description Unit Min Max READ CYCLE t Read Cycle Time 45 ns RC t Address to Data Valid 45 ns AA t Data Hold from Address Change 10 ns OHA t CE LOW and CE HIGH to Data Valid 45 ns ACE 1 2 t OE LOW to Data Valid 22 ns DOE [15] t OE LOW to LOW-Z 5ns LZOE [15, 16] t OE HIGH to High-Z 18 ns HZOE [15] t CE LOW and CE HIGH to Low-Z 10 ns LZCE 1 2 [15, 16] t CE HIGH and CE LOW to High-Z 18 ns HZCE 1 2 t CE L
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® CY62167E MoBL Switching Waveforms [18, 19] Figure 1 shows address transition controlled read cycle waveforms. Figure 1. Read Cycle No. 1 t RC RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [19, 20] Figure 2 shows OE controlled read cycle waveforms. Figure 2. Read Cycle No. 2 ADDRESS t RC CE 1 t PD t HZCE CE 2 t ACE BHE/BLE t DBE t HZBE t LZBE OE t HZOE t DOE t LZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA OUT DATA VALID t LZCE I t CC PU V CC 50% 50% SUPPLY I SB CURRENT Notes 18. The
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® CY62167E MoBL Switching Waveforms (continued) [17, 21, 22] Figure 3 shows WE controlled write cycle waveforms. Figure 3. Write Cycle No. 1 t WC ADDRESS t SCE CE 1 CE 2 t t AW HA t t SA PWE WE t BW BHE/BLE OE t HD t SD NOTE 23 DATA IO VALID DATA t HZOE Notes 21. Data IO is high impedance if OE = V . IH 22. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state. 1 2 IH 23. During this period the IOs are in output state and input signals must not
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® CY62167E MoBL Switching Waveforms (continued) [17, 21, 22] Figure 4 shows CE or CE controlled write cycle waveforms. 1 2 Figure 4. Write Cycle No. 2 t WC ADDRESS t SCE CE 1 CE 2 t SA t t AW HA t PWE WE t BW BHE/BLE OE t HD t SD DATA IO NOTE 23 VALID DATA t HZOE [22] Figure 5 shows WE controlled, OE LOW write cycle waveforms. Figure 5. Write Cycle No. 3 t WC ADDRESS t SCE CE 1 CE 2 t BW BHE/BLE t t AW HA t t SA PWE WE t t SD HD DATA IO NOTE 23 VALID DATA t LZWE t HZWE Document #: 001-15607 Rev.
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® CY62167E MoBL Switching Waveforms (continued) [22] Figure 6 shows BHE/BLE controlled, OE LOW write cycle waveforms. Figure 6. Write Cycle No. 4 t WC ADDRESS CE 1 CE 2 t SCE t t AW HA t BW BHE/BLE t SA t PWE WE t t SD HD DATA IO NOTE 23 VALID DATA Document #: 001-15607 Rev. *A Page 9 of 12 [+] Feedback [+] Feedback [+] Feedback
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® CY62167E MoBL Truth Table CE CE WE OE BHE BLE Inputs Outputs Mode Power 1 2 H X X X X X High-Z Deselect/Power Down Standby (I ) SB X L X X X X High-Z Deselect/Power Down Standby (I ) SB X X X X H H High-Z Deselect/Power Down Standby (I ) SB L H H L L L Data Out (IO –IO ) Read Active (I ) 0 15 CC L H H L H L Data Out (IO –IO ); Read Active (I ) 0 7 CC High-Z (IO –IO ) 8 15 L H H L L H High-Z (IO –IO ); Read Active (I ) 0 7 CC Data Out (IO –IO ) 8 15 L H H H L H High-Z Output Disabled Active (I
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® CY62167E MoBL Package Diagram Figure 7. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183 DIMENSIONS IN INCHES[MM] MIN. MAX. JEDEC # MO-142 0.037[0.95] 0.041[1.05] 1 N 0.020[0.50] TYP. 0.472[12.00] 0.007[0.17] 0.011[0.27] 0.002[0.05] 0.006[0.15] 0.724 [18.40] 0.047[1.20] MAX. 0.787[20.00] 0.004[0.10] 0.010[0.25] 0.008[0.21] GAUGE PLANE 0.020[0.50] 51-85183-*A 0°-5° 0.028[0.70] Document #: 001-15607 Rev. *A Page 11 of 12 © Cypress Semiconductor Corporation, 2007. The information contained here
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® CY62167E MoBL Document History Page ® Document Title: CY62167E MoBL 16-Mbit (1M x 16 / 2M x 8) Static RAM Document Number: 001-15607 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 1103145 See ECN VKN New Data Sheet *A 1138903 See ECN VKN Converted from preliminary to final Changed I spec from 2.8 mA to 4.0 mA for f=1MHz CC(max) Changed I spec from 22 mA to 25 mA for f=f CC(typ) max Changed I spec from 25 mA to 30 mA for f=f CC(max) max Added footnote# 8 related to V IL Chang
