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CY14B256K
256 Kbit (32K x 8) nvSRAM with Real Time Clock
■ High reliability
Features
❐ Endurance to 200K cycles
■ 25 ns, 35 ns, and 45 ns access times
❐ Data retention: 20 years at 55 °C
■ Pin compatible with STK17T88 ■ Single 3V operation with tolerance of +20%, -10%
■ Data integrity of Cypress nvSRAM combined with full featured
■ Commercial and industrial temperature
Real Time Clock
■ 48-Pin SSOP (ROHS compliant)
❐ Low power, 350 nA RTC current
❐ Capacitor or battery backup for RTC
Functional
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CY14B256K Pin Configurations Figure 1. 48-Pin SSOP 48 V 1 V CAP CC 2 47 NC NC A 46 14 3 HSB A 12 4 45 WE A 7 5 44 A 13 A 6 6 43 A 8 A 42 A 5 7 9 INT 8 41 NC A 40 4 9 A 11 10 39 NC NC 48-SSOP 38 NC 11 NC 37 12 NC NC Top View 36 V 13 V SS SS (Not To Scale) 14 35 NC NC V 15 34 V RTCbat RTCcap DQ0 33 DQ 16 6 A 17 32 3 OE A 18 31 A 2 10 A 1 19 30 CE A 20 29 0 DQ7 DQ1 28 21 DQ5 DQ2 22 27 DQ4 X 26 DQ3 23 1 25 24 V X CC 2 Pin Definitions Pin Name Alt IO Type Description A –A Input Address Inputs. Used
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CY14B256K automatically disconnects the V pin from V . A STORE Device Operation CAP CC operation is initiated with power provided by the V capacitor. CAP The CY14B256K nvSRAM consists of two functional Figure 2. AutoStore Mode components paired in the same physical cell. The components are SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data V CC in the SRAM is transferred to the nonvolatile cell (the STORE V V CC CAP operation),
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CY14B256K t , multiple SRAM READ operations take place. If a WRITE It is important to use READ cycles and not WRITE cycles in the DELAY is in progress when HSB is pulled LOW, it allows a time, t , sequence, although it is not necessary that OE be LOW for a DELAY to complete. However, any SRAM WRITE cycles requested after valid sequence. After the t cycle time is fulfilled, the SRAM STORE HSB goes LOW are inhibited until HSB returns HIGH. is activated again for READ and WRITE operations. During a
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CY14B256K Low Average Active Power Best Practices CMOS technology provides the CY14B256K the benefit of nvSRAM products have been used effectively for over 15 years. drawing significantly less current when it is cycled at times longer While ease-of-use is one of the product’s main system values, than 50 ns. Figure 3 shows the relationship between I and experience gained working with hundreds of applications has CC READ and/or WRITE cycle time. Worst case current resulted in the following suggest
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CY14B256K Table 1. Mode Selection A13–A0 Mode IO Power CE WE OE H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active [1, 2, 3] L H L 0x0E38 Read SRAM Output Data Active I CC2 0x31C7 Read SRAM Output Data 0x03E0 Read SRAM Output Data 0x3C1F Read SRAM Output Data 0x303F Read SRAM Output Data 0x0FC0 Nonvolatile STORE Output High Z [1, 2, 3] L H L 0x0E38 Read SRAM Output Data Active 0x31C7 Read SRAM Output Data 0x03E0 Read SRAM Output
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CY14B256K clock operation with the primary source removed, the data stored Real Time Clock Operation in the nvSRAM is secure, having been stored in the nonvolatile elements when power was lost. nvTIME Operation During backup operation, the CY14B256K consumes a The CY14B256K consists of internal registers that contain clock, maximum of 300 nanoamps at 2 volts. The user should choose alarm, watchdog, interrupt, and control functions. RTC registers capacitor or battery values according to the appl
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CY14B256K the match process. Depending on the match bits, the alarm Calibrating the Clock occurs as specifically as once a month or as frequently as once The RTC is driven by a quartz controlled oscillator with a nominal every minute. Selecting none of the match bits (all 1s) indicates frequency of 32.768 kHz. Clock accuracy depends on the quality that no match is required and therefore, alarm is disabled. of the crystal and calibration. The crystal oscillators typically Selecting all match bits
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CY14B256K register is enabled (set to ‘1’). After an interrupt source is active, Figure 4. Watchdog Timer Block Diagram two programmable bits, H/L and P/L, determine the behavior of the output pin driver on INT pin. These two bits are located in the Interrupt register and can be used to drive level or pulse mode output from the INT pin. In pulse mode, the pulse width is internally fixed at approximately 200 ms. This mode is intended Clock Oscillator 1 Hz Divider to reset a host microcontroller.
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CY14B256K Figure 5. Interrupt Block Diagram WDF Watchdog Timer WIE WDF - Watchdog Timer Flag WIE - Watchdog Interrupt V P/L CC Enable PF PF - Power Fail Flag Power Pin PFE - Power Fail Enable Monitor INT PFE Driver AF - Alarm Flag VINT AIE - Alarm Interrupt Enable H/L V SS P/L - Pulse Level H/L - High/Low AF Clock Alarm AIE Figure 6. RTC Recommended Component Configuration DQ 0 A 3 A 2 A 1 A 0 X 1 X 2 Recommended Values: Y1 = 32.768KHz RF = 10M Ohm C1 = 0 (install cap footprint, but leave unl
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CY14B256K [5, 6] Table 3. RTC Register Map [5] BCD Format Data Register Function/Range D7 D6 D5 D4 D3 D2 D1 D0 0x7FFF 10s Years Years Years: 00–99 0x7FFE 0 0 0 10s Months Months Months: 01–12 0x7FFD 0 0 10s Day of Month Day Of Month Day of Month: 01–31 0x7FFC 0 0 0 0 0 Day of Week Day of Week: 01–07 0x7FFB 0 0 10s Hours Hours Hours: 00–23 0x7FFA 0 10s Minutes Minutes Minutes: 00–59 0x7FF9 0 10s Seconds Seconds Seconds: 00–59 [7] 0x7FF8 OSCEN 0 Cal Sign Calibration (00000) Calibration Values (
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CY14B256K Table 4. Register Map Detail Time Keeping - Years D7 D6 D5 D4 D3 D2 D1 D0 0x7FFF 10s Years Years Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99. Time Keeping - Months D7 D6 D5 D4 D3 D2 D1 D0 0x7FFE 0 0 0 10s Month Months Contains the BCD digits of the month. Lower nibble (four bits) contains the lower
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CY14B256K Table 4. Register Map Detail (continued) Calibration/Control D7 D6 D5 D4 D3 D2 D1 D0 0X7FF8 OSCEN 0 Calibration Calibration Sign OSCEN Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs. Disabling the oscillator saves battery or capacitor power during storage. Calibration Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base. Sign Calibration These five bits control the calibr
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CY14B256K Table 4. Register Map Detail (continued) Alarm - Hours D7 D6 D5 D4 D3 D2 D1 D0 0x7FF4 M 10s Alarm Hours Alarm Hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value. M Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the hours value. Alarm - Minutes D7 D6 D5 D4 D3 D2 D1 D0 0x7FF3 M 10s Alarm Minutes Alarm Minutes Contains the alarm value for the minutes a
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CY14B256K Package Power Dissipation Maximum Ratings Capability (T = 25°C) ................................................... 1.0W A Exceeding maximum ratings may impair the useful life of the Surface Mount Pb Soldering device. These user guidelines are not tested. Temperature (3 Seconds).......................................... +260 °C Storage Temperature ................................. –65 °C to +150 °C DC Output Current (1 output at a time, 1s duration) ... 15 mA Ambient Temperature with
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CY14B256K Data Retention and Endurance Parameter Description Min Unit DATA Data Retention 20 Years R NV Nonvolatile STORE Operations 200 K C Capacitance These parameters are guaranteed but not tested. Parameter Description Test Conditions Max Unit Input Capacitance T = 25 °C, f = 1 MHz, C 7pF IN A V = 0 to 3.0 V CC C Output Capacitance 7 pF OUT Thermal Resistance These parameters are guaranteed but not tested. Parameter Description Test Conditions 48-SSOP Unit Θ Thermal Resistance Test conditi
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CY14B256K AC Switching Characteristics Parameter 25 ns 35 ns 45 ns Description Unit Cypress Alt. Min Max Min Max Min Max Parameter Parameter SRAM Read Cycle t t Chip Enable Access Time 25 35 45 ns ACE ELQV [10] t t t Read Cycle Time 25 35 45 ns RC AVAV, ELEH [11] t t Address Access Time 25 35 45 ns AA AVQV t t Output Enable to Data Valid 12 15 20 ns DOE GLQV [11] t t Output Hold After Address Change 3 3 3 ns OHA AXQX [12] t t Chip Enable to Output Active 3 3 3 ns LZCE ELQX [12] t t Chip Disable
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CY14B256K AC Switching Characteristics (continued) Parameter 25 ns 35 ns 45 ns Description Unit Cypress Alt. Min Max Min Max Min Max Parameter Parameter SRAM Write Cycle t t Write Cycle Time 25 35 45 ns WC AVAV t t t Write Pulse Width 20 25 30 ns PWE WLWH, WLEH t t t Chip Enable To End of Write 20 25 30 ns SCE ELWH, ELEH t t t Data Setup to End of Write 10 12 15 ns SD DVWH, DVEH t t t Data Hold After End of Write 0 0 0 ns HD WHDX, EHDX t t t Address Setup to End of Write 20 25 30 ns AW AVWH, AVE
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CY14B256K AutoStore or Power Up RECALL CY14B256K Parameter Description Unit Min Max [17] t Power Up RECALL Duration 40 ms HRECALL [18, 19] t STORE Cycle Duration Commercial 12.5 ms STORE Industrial 15 ms V Low Voltage Trigger Level 2.65 V SWITCH t VCC Rise Time 150 μs VCCRISE Figure 12. AutoStore/Power Up RECALL STORE occurs only No STORE occurs without atleast one if a SRAM write has happened SRAM write V CC V SWITCH t VCCRISE AutoStore t t STORE STORE POWER-UP RECALL t t HRECALL HRECALL R
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CY14B256K [20, 21] Software Controlled STORE/RECALL Cycles 25 ns 35 ns 45 ns Alt. Parameter Description Unit Parameter Min Max Min Max Min Max t t STORE/RECALL Initiation Cycle Time 25 35 45 ns RC AVAV t t Address Setup Time 0 0 0 ns SA AVEL t t Clock Pulse Width 20 25 30 ns CW ELEH t t Address Hold Time 1 1 1 ns HA EHAX t RECALL Duration 170 170 170 μs RECALL [21] Controlled Software STORE/RECALL Cycle Figure 13. CE t t RC RC ADDRESS # 1 ADDRESS # 6 ADDRESS t t SA SCE CE t HA OE tSTORE /
