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SPARC JPS1
Implementation Supplement:
Fujitsu SPARC64 V
Fujitsu Limited
Release 1.0, 1 July 2002
Fujitsu Limited
4-1-1 Kamikodanaka
Nahahara-ku, Kawasaki, 211-8588
Japan
Part No. 806-6755-1.0
ページ2に含まれる内容の要旨
Copyright 2002 Sun Microsystems, Inc., 901 San Antonio Road, Palo Alto, California 94303 U.S.A. All rights reserved. Portions of this document are protected by copyright 1994 SPARC International, Inc. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution, and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. T
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3 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
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F.CHAPTER Contents 1. Overview 1 Navigating the SPARC64 V Implementation Supplement 1 Fonts and Notational Conventions 1 The SPARC64 V processor 2 Component Overview 4 Instruction Control Unit (IU) 6 Execution Unit (EU) 6 Storage Unit (SU) 7 Secondary Cache and External Access Unit (SXU) 8 2. Definitions 9 3. Architectural Overview 13 4. Data Formats 15 5. Registers 17 Nonprivileged Registers 17 Floating-Point State Register (FSR) 18 Tick (TICK) Register 19 Privileged Registers 19 Trap State (TS
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Floating-Point Deferred-Trap Queue (FQ) 24 IU Deferred-Trap Queue 24 6. Instructions 25 Instruction Execution 25 Data Prefetch 25 Instruction Prefetch 26 Syncing Instructions 27 Instruction Formats and Fields 28 Instruction Categories 29 Control-Transfer Instructions (CTIs) 29 Floating-Point Operate (FPop) Instructions 30 Implementation-Dependent Instructions 30 Processor Pipeline 31 Instruction Fetch Stages 31 Issue Stages 33 Execution Stages 33 Completion Stages 34 7. Traps 35 Processor States
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SPARC JPS1 Implementation-Dependent Traps 39 8. Memory Models 41 Overview 42 SPARC V9 Memory Model 42 Mode Control 42 Synchronizing Instruction and Data Memory 42 A. Instruction Definitions: SPARC64 V Extensions 45 Block Load and Store Instructions (VIS I) 47 Call and Link 49 Implementation-Dependent Instructions 49 Floating-Point Multiply-Add/Subtract 50 Jump and Link 53 Load Quadword, Atomic [Physical] 54 Memory Barrier 55 Partial Store (VIS I) 57 Prefetch Data 57 Read State Register 58 SHUTD
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D. Formal Specification of the Memory Models 81 E. Opcode Maps 83 F. Memory Management Unit 85 Virtual Address Translation 85 Translation Table Entry (TTE) 86 TSB Organization 88 TSB Pointer Formation 88 Faults and Traps 89 Reset, Disable, and RED_state Behavior 91 Internal Registers and ASI operations 92 Accessing MMU Registers 92 I/D TLB Data In, Data Access, and Tag Read Registers 93 I/D TSB Extension Registers 97 I/D Synchronous Fault Status Registers (I-SFSR, D-SFSR) 97 MMU Bypass 104 TLB R
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Level-1 Data Cache (L1D Cache) 127 Level-2 Unified Cache (L2 Cache) 127 Cache Coherency Protocols 128 Cache Control/Status Instructions 128 Flush Level-1 Instruction Cache (ASI_FLUSH_L1I) 129 Level-2 Cache Control Register (ASI_L2_CTRL) 130 L2 Diagnostics Tag Read (ASI_L2_DIAG_TAG_READ) 130 L2 Diagnostics Tag Read Registers (ASI_L2_DIAG_TAG_READ_REG) 131 N. Interrupt Handling 133 Interrupt Dispatch 133 Interrupt Receive 135 Interrupt Global Registers 136 Interrupt-Related ASR Registers 136 Inter
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error_state Transition Error 150 Urgent Error 150 Restrainable Error 152 Action and Error Control 153 Registers Related to Error Handling 153 Summary of Actions Upon Error Detection 154 Extent of Automatic Source Data Correction for Correctable Error 157 Error Marking for Cacheable Data Error 157 ASI_EIDR 161 Control of Error Action (ASI_ERROR_CONTROL) 161 Fatal Error and error_state Transition Error 163 ASI_STCHG_ERROR_INFO 163 Fatal Error Types 164 Types of error_state Transition Errors 164 Ur
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TLB Error Handling 195 Handling of TLB Entry Errors 195 Automatic Way Reduction of sTLB 196 Handling of Extended UPA Bus Interface Error 197 Handling of Extended UPA Address Bus Error 197 Handling of Extended UPA Data Bus Error 197 Q. Performance Instrumentation 201 Performance Monitor Overview 201 Sample Pseudocodes 201 Performance Monitor Description 203 Instruction Statistics 204 Trap-Related Statistics 206 MMU Event Counters 207 Cache Event Counters 208 UPA Event Counters 210 Miscellaneous C
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viii SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V Release 1.0, 1 July 2002
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F.CHAPTER 1 Overview 1.1 Navigating the SPARC64 V Implementation Supplement We suggest that you approach this Implementation Supplement SPARC Joint Programming Specification as follows. 1. Familiarize yourself with the SPARC64 V processor and its components by reading these sections: The SPARC64 V processor on page 2 Component Overview on page 4 Processor Pipeline on page 31 2. Study the terminology in Chapter 2, Definitions: 3. For details of architectural changes, see the remaining
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1.3 The SPARC64 V processor The SPARC64 V processor is a high-performance, high-reliability, and high-integrity processor that fully implements the instruction set architecture that conforms to SPARC V9, as described in JPS1 Commonality. In addition, the SPARC64 V processor implements the following features: 64-bit virtual address space and 43-bit physical address space Advanced RAS features that enable high-integrity error handling Microarchitecture for High Performance The SPARC64 V is
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1. Advanced RAS features for caches Strong cache error protection: ECC protection for D1 (Data level 1) cache data, U2 (unified level 2) cache data, and the U2 cache tag. Parity protection for I1 (Instruction level 1) cache data. Parity protection and duplication for the I1 cache tag and the D1 cache tag. Automatic correction of all types of single-bit error: Automatic single-bit error correction for the ECC protected data. Invalidation and refilling of I1 cache data for the I1 ca
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Asynchronous data error (ADE) trap for additional errors: Relaxed instruction end method (precise, retryable, not retryable) for the async_data_error exception to indicate how the instruction should end; depends on the executing instruction and the detected error. Some ADE traps that are deferred but retryable. Simultaneous reporting of all detected ADE errors at the error barrier for correct handling of retryability. 1.3.1 Component Overview The SPARC64 V processor contains these com
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Extended UPA Bus SX-Unit E-Unit UPA interface logic MoveIn buffer MoveOut buffer U2$ U2$ data ALUs ALU tag 2M 4-way Input EXA Registers S-Unit interface EXB and FLA Output FLB Registers S-Unit EAGA EAGB SX interface SX order queue Store queue GUB FUB I-TLB tag data D-TLB tag data 2048 2048 Level-1 I cache GPR FPR Level-1 D cache + 32 + 32 128 KB, 2-way 128 KB, 2-way entry entry I-Unit E-unit Commit stack entry Instruction Instruction
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1.3.2 Instruction Control Unit (IU) The IU predicts the instruction execution path, fetches instructions on the predicted path, distributes the fetched instructions to appropriate reservation stations, and dispatches the instructions to the execution pipeline. The instructions are executed out of order, and the IU commits the instructions in order. Major blocks are defined in TABLE 1-1. TABLE 1-1 Instruction Control Unit Major Blocks Name Description Instruction fetch pipeline Five stages: f
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TABLE 1-2 Execution Unit Major Blocks (Continued) Name Description Interface registers Input/output registers to other units. Two integer execution pipelines 64-bit ALU and shifters. (EXA, EXB) Two floating-point and graphics Each floating-point execution pipeline can execute floating execution pipelines (FLA, FLB) point multiply, floating point add/sub, floating-point multiply and add, floating point div/sqrt, and floating- point graphics instruction. Two virtual address adders for Two 64-bi
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1.3.5 Secondary Cache and External Access Unit (SXU) The SXU controls the operation of unified level-2 caches and the external data access interface (extended UPA interface). TABLE 1-4 describes the major blocks of the SXU. TABLE 1-4 Secondary Cache and External Access Unit Major Blocks Name Description Unified level-2 cache 2-Mbyte, 4-way associative, 64-byte line, writeback; provides low latency data source for both instruction level-1 cache and data level-1 cache. Movein buffer Sixteen ent
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F.CHAPTER 2 Definitions This chapter defines concepts unique to the SPARC64 V, the Fujitsu implementation of SPARC JPS1. For definition of terms that are common to all implementations, please refer to Chapter 2 of Commonality. committed Term applied to an instruction when it has completed without error and all prior instructions have completed without error and have been committed. When an instruction is committed, the state of the machine is permanently changed to reflect the result of the
